@@ -1395,27 +1395,6 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
13951395 MachineInstr &NewMI = *std::prev (MII);
13961396 NewMI.setDebugLoc (DL);
13971397
1398- // In a situation like the following:
1399- //
1400- // undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable),
1401- // ; DefSubIdx = subreg
1402- // %3:reg = COPY %2 ; SrcIdx = DstIdx = 0
1403- // .... = SOMEINSTR %3:reg
1404- //
1405- // there are no subranges for %3 so after rematerialization we need
1406- // to explicitly create them. Undefined subranges are removed later on.
1407- if (DstReg.isVirtual () && DefSubIdx && !CP.getSrcIdx () && !CP.getDstIdx () &&
1408- MRI->shouldTrackSubRegLiveness (DstReg)) {
1409- LiveInterval &DstInt = LIS->getInterval (DstReg);
1410- if (!DstInt.hasSubRanges ()) {
1411- LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg (DstReg);
1412- LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask (DefSubIdx);
1413- LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
1414- DstInt.createSubRangeFrom (LIS->getVNInfoAllocator (), UsedLanes, DstInt);
1415- DstInt.createSubRangeFrom (LIS->getVNInfoAllocator (), UnusedLanes, DstInt);
1416- }
1417- }
1418-
14191398 // In a situation like the following:
14201399 // %0:subreg = instr ; DefMI, subreg = DstIdx
14211400 // %1 = copy %0:subreg ; CopyMI, SrcIdx = 0
@@ -1544,6 +1523,26 @@ bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
15441523 // sure that "undef" is not set.
15451524 if (NewIdx == 0 )
15461525 NewMI.getOperand (0 ).setIsUndef (false );
1526+
1527+ // In a situation like the following:
1528+ //
1529+ // undef %2.subreg:reg = INST %1:reg ; DefMI (rematerializable),
1530+ // ; DefSubIdx = subreg
1531+ // %3:reg = COPY %2 ; SrcIdx = DstIdx = 0
1532+ // .... = SOMEINSTR %3:reg
1533+ //
1534+ // there are no subranges for %3 so after rematerialization we need
1535+ // to explicitly create them. Undefined subranges are removed later on.
1536+ if (DefSubIdx && !CP.getSrcIdx () && !CP.getDstIdx () &&
1537+ MRI->shouldTrackSubRegLiveness (DstReg) && !DstInt.hasSubRanges ()) {
1538+ LaneBitmask FullMask = MRI->getMaxLaneMaskForVReg (DstReg);
1539+ LaneBitmask UsedLanes = TRI->getSubRegIndexLaneMask (DefSubIdx);
1540+ LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
1541+ VNInfo::Allocator &Alloc = LIS->getVNInfoAllocator ();
1542+ DstInt.createSubRangeFrom (Alloc, UsedLanes, DstInt);
1543+ DstInt.createSubRangeFrom (Alloc, UnusedLanes, DstInt);
1544+ }
1545+
15471546 // Add dead subregister definitions if we are defining the whole register
15481547 // but only part of it is live.
15491548 // This could happen if the rematerialization instruction is rematerializing
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