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Vitaly Cheptsovtstellar
Vitaly Cheptsov
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tstellar
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[RISCV] Support emulated TLS
As discussed earlier in the [GitHub issue](#59500), currently LLVM generates invalid code when emulated TLS is used. There were attempts to resolve this previously (D102527), but they were not merged because the component owners raised concerns about emulated TLS efficiency. The current state of the art is that: - OpenBSD team, which raised the initial issue, simply has [patches downstream](https://github.com/openbsd/src/blob/a0747c9/gnu/llvm/llvm/lib/Target/RISCV/RISCVISelLowering.cpp#L2850-L2852). - Our team, which raised the GH issue, has patches downstream as well. We also do not use `malloc` or any [dynamic allocations](#59500 (comment)) with emulated TLS, so the concerns raised in the original issue does not apply to us. - GCC compatibility is broken, because GCC supports emulated TLS. - RISC-V is the only architecture in LLVM that does not support emulated TLS, and work is being done to at least warn the users about it (D143619). With all these in mind I believe it is important to address the consumers' needs especially given that there is little to no maintenance downsides. Differential Revision: https://reviews.llvm.org/D143708 (cherry picked from commit f5e63f8)
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -4540,6 +4540,9 @@ SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
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GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
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assert(N->getOffset() == 0 && "unexpected offset in global node");
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if (DAG.getTarget().useEmulatedTLS())
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return LowerToTLSEmulatedModel(N, DAG);
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TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal());
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if (DAG.getMachineFunction().getFunction().getCallingConv() ==

‎llvm/test/CodeGen/RISCV/emutls.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -emulated-tls -relocation-model=pic < %s \
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; RUN: | FileCheck -check-prefix=RV32 %s
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; RUN: llc -mtriple=riscv64 -emulated-tls -relocation-model=pic < %s \
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; RUN: | FileCheck -check-prefix=RV64 %s
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@external_x = external thread_local global i32, align 8
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@y = thread_local global i8 7, align 2
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@internal_z = internal thread_local global i64 9, align 16
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define ptr @get_external_x() nounwind {
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; RV32-LABEL: get_external_x:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: .Lpcrel_hi0:
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; RV32-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.external_x)
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; RV32-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi0)(a0)
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; RV32-NEXT: call __emutls_get_address@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: get_external_x:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: .Lpcrel_hi0:
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; RV64-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.external_x)
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; RV64-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi0)(a0)
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; RV64-NEXT: call __emutls_get_address@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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entry:
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ret ptr @external_x
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}
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define ptr @get_y() nounwind {
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; RV32-LABEL: get_y:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: .Lpcrel_hi1:
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; RV32-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.y)
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; RV32-NEXT: lw a0, %pcrel_lo(.Lpcrel_hi1)(a0)
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; RV32-NEXT: call __emutls_get_address@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: get_y:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: .Lpcrel_hi1:
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; RV64-NEXT: auipc a0, %got_pcrel_hi(__emutls_v.y)
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; RV64-NEXT: ld a0, %pcrel_lo(.Lpcrel_hi1)(a0)
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; RV64-NEXT: call __emutls_get_address@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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entry:
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ret ptr @y
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}
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define ptr @get_internal_z() nounwind {
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; RV32-LABEL: get_internal_z:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: addi sp, sp, -16
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; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32-NEXT: .Lpcrel_hi2:
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; RV32-NEXT: auipc a0, %pcrel_hi(__emutls_v.internal_z)
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; RV32-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2)
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; RV32-NEXT: call __emutls_get_address@plt
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; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 16
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; RV32-NEXT: ret
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;
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; RV64-LABEL: get_internal_z:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: addi sp, sp, -16
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; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64-NEXT: .Lpcrel_hi2:
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; RV64-NEXT: auipc a0, %pcrel_hi(__emutls_v.internal_z)
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; RV64-NEXT: addi a0, a0, %pcrel_lo(.Lpcrel_hi2)
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; RV64-NEXT: call __emutls_get_address@plt
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; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 16
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; RV64-NEXT: ret
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entry:
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ret ptr @internal_z
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}
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; UTC_ARGS: --disable
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; RV32: .data
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; RV32: .globl __emutls_v.y
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; RV32: .p2align 2
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; RV32-LABEL: __emutls_v.y:
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; RV32-NEXT: .word 1
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; RV32-NEXT: .word 2
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; RV32-NEXT: .word 0
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; RV32-NEXT: .word __emutls_t.y
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; RV32: .section .rodata,
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; RV32-LABEL: __emutls_t.y:
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; RV32-NEXT: .byte 7
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; RV32: .data
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; RV32: .p2align 2
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; RV32-LABEL: __emutls_v.internal_z:
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; RV32-NEXT: .word 8
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; RV32-NEXT: .word 16
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; RV32-NEXT: .word 0
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; RV32-NEXT: .word __emutls_t.internal_z
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; RV32: .section .rodata,
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; RV32-LABEL: __emutls_t.internal_z:
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; RV32-NEXT: .quad 9
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; RV64: .data
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; RV64: .globl __emutls_v.y
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; RV64: .p2align 3
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; RV64-LABEL: __emutls_v.y:
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; RV64-NEXT: .quad 1
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; RV64-NEXT: .quad 2
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; RV64-NEXT: .quad 0
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; RV64-NEXT: .quad __emutls_t.y
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; RV64: .section .rodata,
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; RV64-LABEL: __emutls_t.y:
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; RV64-NEXT: .byte 7
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; RV64: .data
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; RV64: .p2align 3
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; RV64-LABEL: __emutls_v.internal_z:
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; RV64-NEXT: .quad 8
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; RV64-NEXT: .quad 16
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; RV64-NEXT: .quad 0
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; RV64-NEXT: .quad __emutls_t.internal_z
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; RV64: .section .rodata,
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; RV64-LABEL: __emutls_t.internal_z:
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; RV64-NEXT: .quad 9

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