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[AArch64] Add assembly/disassembly for {S,U,SU,US}TMOPA instructions
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‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td‎

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@@ -158,6 +158,15 @@ let Predicates = [HasSME2p2, HasSMEI16I64] in {
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defm USMOP4S : sme_quarter_outer_product_i64<0b1, 0b0, 0b1, "usmop4s">;
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}
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let Predicates = [HasSME2p2] in {
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def STMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b00100, ZZ_b_mul_r, ZPR8, "stmopa">;
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def STMOPA_M2ZZZI_HtoS : sme_int_sparse_outer_product_i32<0b00101, ZZ_h_mul_r, ZPR16, "stmopa">;
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def UTMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b11100, ZZ_b_mul_r, ZPR8, "utmopa">;
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def UTMOPA_M2ZZZI_HtoS : sme_int_sparse_outer_product_i32<0b10101, ZZ_h_mul_r, ZPR16, "utmopa">;
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def SUTMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b01100, ZZ_b_mul_r, ZPR8, "sutmopa">;
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def USTMOPA_M2ZZZI_BtoS : sme_int_sparse_outer_product_i32<0b10100, ZZ_b_mul_r, ZPR8, "ustmopa">;
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}
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let Predicates = [HasSME] in {
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//===----------------------------------------------------------------------===//
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// Loads and stores

‎llvm/lib/Target/AArch64/SMEInstrFormats.td‎

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@@ -390,6 +390,35 @@ multiclass sme_int_outer_product_i64<bits<3> opc, string mnemonic,
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def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, op, timm32_0_7, nxv8i1, nxv8i16>;
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}
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class sme_int_sparse_outer_product_i32<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
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: I<(outs TileOp32:$ZAda),
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(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
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mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
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"", []>,
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Sched<[]> {
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bits<2> ZAda;
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bits<4> Zn;
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bits<5> Zm;
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bits<3> Zk;
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bits<2> imm;
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let Inst{31-25} = 0b1000000;
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let Inst{24} = opc{4};
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let Inst{23-22} = 0b01;
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let Inst{21} = opc{3};
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let Inst{20-16} = Zm;
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let Inst{15} = opc{2};
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let Inst{14} = 0b0;
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let Inst{13} = opc{1};
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let Inst{12-10} = Zk;
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let Inst{9-6} = Zn;
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let Inst{5-4} = imm;
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let Inst{3} = opc{0};
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let Inst{2} = 0b0;
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let Inst{1-0} = ZAda;
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let Constraints = "$ZAda = $_ZAda";
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}
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class sme_outer_product_widening_inst<bits<3> opc, ZPRRegOp zpr_ty, string mnemonic>
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: I<(outs TileOp32:$ZAda),
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(ins TileOp32:$_ZAda, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn, zpr_ty:$Zm),

‎llvm/test/MC/AArch64/SME2p2/stmopa-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid ZA register
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stmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: stmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za4.s, {z30.h-z31.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: stmopa za4.s, {z30.h-z31.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list operand
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stmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: stmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za3.s, {z29.h-z30.h}, z31.h, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: stmopa za3.s, {z29.h-z30.h}, z31.h, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZK register
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stmopa za3.s, {z28.b-z29.b}, z31.b, z27[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: stmopa za3.s, {z28.b-z29.b}, z31.b, z27[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za3.s, {z28.h-z29.h}, z31.h, z24[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: stmopa za3.s, {z28.h-z29.h}, z31.h, z24[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za3.s, {z28.h-z29.h}, z31.h, z27[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: stmopa za3.s, {z28.h-z29.h}, z31.h, z27[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid immediate
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stmopa za3.s, {z28.b-z29.b}, z31.b, z20[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: stmopa za3.s, {z28.b-z29.b}, z31.b, z20[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za3.s, {z28.h-z29.h}, z31.h, z20[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: stmopa za3.s, {z28.h-z29.h}, z31.h, z20[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZPR type suffix
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stmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: stmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: stmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: stmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: stmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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stmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: stmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SME2p2/stmopa.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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stmopa za0.s, {z0.b-z1.b}, z0.b, z20[0] // 10000000-01000000-10000000-00000000
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// CHECK-INST: stmopa za0.s, { z0.b, z1.b }, z0.b, z20[0]
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// CHECK-ENCODING: [0x00,0x80,0x40,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80408000 <unknown>
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stmopa za3.s, {z12.b-z13.b}, z8.b, z23[3] // 10000000-01001000-10001101-10110011
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// CHECK-INST: stmopa za3.s, { z12.b, z13.b }, z8.b, z23[3]
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// CHECK-ENCODING: [0xb3,0x8d,0x48,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80488db3 <unknown>
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stmopa za3.s, {z30.b-z31.b}, z31.b, z31[3] // 10000000-01011111-10011111-11110011
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// CHECK-INST: stmopa za3.s, { z30.b, z31.b }, z31.b, z31[3]
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// CHECK-ENCODING: [0xf3,0x9f,0x5f,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 805f9ff3 <unknown>
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stmopa za0.s, {z0.h-z1.h}, z0.h, z20[0] // 10000000-01000000-10000000-00001000
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// CHECK-INST: stmopa za0.s, { z0.h, z1.h }, z0.h, z20[0]
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// CHECK-ENCODING: [0x08,0x80,0x40,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80408008 <unknown>
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stmopa za3.s, {z12.h-z13.h}, z8.h, z23[3] // 10000000-01001000-10001101-10111011
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// CHECK-INST: stmopa za3.s, { z12.h, z13.h }, z8.h, z23[3]
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// CHECK-ENCODING: [0xbb,0x8d,0x48,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 80488dbb <unknown>
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stmopa za3.s, {z30.h-z31.h}, z31.h, z31[3] // 10000000-01011111-10011111-11111011
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// CHECK-INST: stmopa za3.s, { z30.h, z31.h }, z31.h, z31[3]
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// CHECK-ENCODING: [0xfb,0x9f,0x5f,0x80]
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// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 805f9ffb <unknown>

‎llvm/test/MC/AArch64/SME2p2/sutmopa-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid ZA register
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sutmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sutmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list operand
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sutmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: sutmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZK register
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sutmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sutmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sutmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid immediate
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sutmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: sutmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
45+
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// --------------------------------------------------------------------------//
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// Invalid ZPR type suffix
48+
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sutmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: sutmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sutmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: sutmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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sutmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sutmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
62+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
63+
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sutmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: sutmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
67+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
68+
69+
sutmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
71+
// CHECK-NEXT: sutmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
73+
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sutmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: sutmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SME2p2/sutmopa.s‎

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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=-sme2p2 --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
10+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p2 -disassemble -show-encoding \
13+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
14+
15+
sutmopa za0.s, {z0.b-z1.b}, z0.b, z20[0] // 10000000-01100000-10000000-00000000
16+
// CHECK-INST: sutmopa za0.s, { z0.b, z1.b }, z0.b, z20[0]
17+
// CHECK-ENCODING: [0x00,0x80,0x60,0x80]
18+
// CHECK-ERROR: instruction requires: sme2p2
19+
// CHECK-UNKNOWN: 80608000 <unknown>
20+
21+
sutmopa za1.s, {z10.b-z11.b}, z21.b, z29[1] // 10000000-01110101-10010101-01010001
22+
// CHECK-INST: sutmopa za1.s, { z10.b, z11.b }, z21.b, z29[1]
23+
// CHECK-ENCODING: [0x51,0x95,0x75,0x80]
24+
// CHECK-ERROR: instruction requires: sme2p2
25+
// CHECK-UNKNOWN: 80759551 <unknown>
26+
27+
sutmopa za3.s, {z30.b-z31.b}, z31.b, z31[3] // 10000000-01111111-10011111-11110011
28+
// CHECK-INST: sutmopa za3.s, { z30.b, z31.b }, z31.b, z31[3]
29+
// CHECK-ENCODING: [0xf3,0x9f,0x7f,0x80]
30+
// CHECK-ERROR: instruction requires: sme2p2
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// CHECK-UNKNOWN: 807f9ff3 <unknown>

‎llvm/test/MC/AArch64/SME2p2/ustmopa-diagnostics.s‎

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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid ZA register
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ustmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ustmopa za4.s, {z30.b-z31.b}, z31.b, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid vector list operand
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ustmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
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// CHECK-NEXT: ustmopa za3.s, {z29.b-z30.b}, z31.b, z31[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZK register
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ustmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z19[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ustmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z24[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ustmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted vector register, expected register in z20..z23 or z28..z31
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// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z27[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid immediate
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ustmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
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// CHECK-NEXT: ustmopa za3.s, {z28.b-z29.b}, z31.b, z29[4]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Invalid ZPR type suffix
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ustmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: ustmopa za0.h, {z28.b-z29.b}, z31.b, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ustmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: ustmopa za0.h, {z28.h-z29.h}, z31.h, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ustmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ustmopa za3.s, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ustmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: ustmopa za3.s, {z28.s-z29.s}, z31.s, z20[2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ustmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: ustmopa za3.d, {z28.s-z29.s}, z31.s, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ustmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3].s
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// CHECK-NEXT: ustmopa za3.d, {z28.h-z29.h}, z31.h, z20[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

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