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author
Thorsten Schütt
committed
second round
1 parent d08de49 commit 55aa772

29 files changed

+661
-2083
lines changed

‎llvm/lib/CodeGen/GlobalISel/CombinerHelperArtifacts.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,7 @@ bool CombinerHelper::matchUnmergeValuesAnyExtBuildVector(const MachineInstr &MI,
113113
bool CombinerHelper::matchUnmergeValuesOfScalarAndVector(const MachineInstr &MI,
114114
BuildFnTy &MatchInfo) {
115115

116-
constexpr unsigned MAX_NUM_DEFS_LIMIT = 8;
116+
constexpr unsigned MAX_NUM_DEFS_LIMIT = 4;
117117

118118
// %opaque:_(<2 x s64>) = G_OPAQUE
119119
// %un1:_(s64), %un2:_(s64) = G_UNMERGE_VALUES %opaque(<2 x s64>)

‎llvm/lib/Target/AArch64/AArch64Combine.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ def AArch64PostLegalizerCombiner
322322
extractvecelt_pairwise_add, redundant_or,
323323
mul_const, redundant_sext_inreg,
324324
form_bitfield_extract, rotate_out_of_range,
325-
icmp_to_true_false_known_bits, vector_ops_combines,
325+
icmp_to_true_false_known_bits,
326326
select_combines, fold_merge_to_zext,
327327
constant_fold_binops, identity_combines,
328328
ptr_add_immed_chain, overlapping_and,

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir‎

Lines changed: 1 addition & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -585,22 +585,7 @@ body: |
585585
bb.1:
586586
; CHECK-LABEL: name: test_long_opaque_vector_scalar
587587
; CHECK: %opaque:_(<8 x s16>) = COPY $q0
588-
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
589-
; CHECK-NEXT: %un1:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C]](s64)
590-
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
591-
; CHECK-NEXT: %un2:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C1]](s64)
592-
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
593-
; CHECK-NEXT: %un3:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C2]](s64)
594-
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
595-
; CHECK-NEXT: %un4:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C3]](s64)
596-
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
597-
; CHECK-NEXT: %un5:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C4]](s64)
598-
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
599-
; CHECK-NEXT: %un6:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C5]](s64)
600-
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
601-
; CHECK-NEXT: %un7:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C6]](s64)
602-
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
603-
; CHECK-NEXT: %un8:_(s16) = G_EXTRACT_VECTOR_ELT %opaque(<8 x s16>), [[C7]](s64)
588+
; CHECK-NEXT: %un1:_(s16), %un2:_(s16), %un3:_(s16), %un4:_(s16), %un5:_(s16), %un6:_(s16), %un7:_(s16), %un8:_(s16) = G_UNMERGE_VALUES %opaque(<8 x s16>)
604589
; CHECK-NEXT: %zext1:_(s32) = G_ZEXT %un1(s16)
605590
; CHECK-NEXT: %zext2:_(s32) = G_ZEXT %un2(s16)
606591
; CHECK-NEXT: %zext3:_(s32) = G_ZEXT %un3(s16)

‎llvm/test/CodeGen/AArch64/abs.ll‎

Lines changed: 8 additions & 83 deletions
Original file line numberDiff line numberDiff line change
@@ -355,66 +355,10 @@ entry:
355355
declare <3 x i8> @llvm.abs.v3i8(<3 x i8>, i1)
356356

357357
define <7 x i8> @abs_v7i8(<7 x i8> %a){
358-
; CHECK-SD-LABEL: abs_v7i8:
359-
; CHECK-SD: // %bb.0: // %entry
360-
; CHECK-SD-NEXT: abs v0.8b, v0.8b
361-
; CHECK-SD-NEXT: ret
362-
;
363-
; CHECK-GI-LABEL: abs_v7i8:
364-
; CHECK-GI: // %bb.0: // %entry
365-
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
366-
; CHECK-GI-NEXT: mov b1, v0.b[1]
367-
; CHECK-GI-NEXT: mov v2.b[0], v0.b[0]
368-
; CHECK-GI-NEXT: mov b3, v0.b[2]
369-
; CHECK-GI-NEXT: mov v2.b[1], v1.b[0]
370-
; CHECK-GI-NEXT: mov b1, v0.b[3]
371-
; CHECK-GI-NEXT: mov v2.b[2], v3.b[0]
372-
; CHECK-GI-NEXT: mov b3, v0.b[4]
373-
; CHECK-GI-NEXT: mov v2.b[3], v1.b[0]
374-
; CHECK-GI-NEXT: mov b1, v0.b[5]
375-
; CHECK-GI-NEXT: mov b0, v0.b[6]
376-
; CHECK-GI-NEXT: mov v2.b[4], v3.b[0]
377-
; CHECK-GI-NEXT: mov v2.b[5], v1.b[0]
378-
; CHECK-GI-NEXT: mov v2.b[6], v0.b[0]
379-
; CHECK-GI-NEXT: abs v0.8b, v2.8b
380-
; CHECK-GI-NEXT: mov b1, v0.b[1]
381-
; CHECK-GI-NEXT: mov b2, v0.b[2]
382-
; CHECK-GI-NEXT: mov b3, v0.b[3]
383-
; CHECK-GI-NEXT: mov b4, v0.b[4]
384-
; CHECK-GI-NEXT: mov b5, v0.b[6]
385-
; CHECK-GI-NEXT: fmov w8, s1
386-
; CHECK-GI-NEXT: mov b1, v0.b[5]
387-
; CHECK-GI-NEXT: mov v0.h[1], w8
388-
; CHECK-GI-NEXT: fmov w8, s2
389-
; CHECK-GI-NEXT: mov v0.h[2], w8
390-
; CHECK-GI-NEXT: fmov w8, s3
391-
; CHECK-GI-NEXT: mov v0.h[3], w8
392-
; CHECK-GI-NEXT: fmov w8, s4
393-
; CHECK-GI-NEXT: mov v0.h[4], w8
394-
; CHECK-GI-NEXT: fmov w8, s1
395-
; CHECK-GI-NEXT: mov v0.h[5], w8
396-
; CHECK-GI-NEXT: fmov w8, s5
397-
; CHECK-GI-NEXT: mov v0.h[6], w8
398-
; CHECK-GI-NEXT: mov h1, v0.h[1]
399-
; CHECK-GI-NEXT: mov h2, v0.h[3]
400-
; CHECK-GI-NEXT: mov h3, v0.h[4]
401-
; CHECK-GI-NEXT: mov h4, v0.h[5]
402-
; CHECK-GI-NEXT: mov h5, v0.h[6]
403-
; CHECK-GI-NEXT: fmov w8, s1
404-
; CHECK-GI-NEXT: mov h1, v0.h[2]
405-
; CHECK-GI-NEXT: mov v0.b[1], w8
406-
; CHECK-GI-NEXT: fmov w8, s1
407-
; CHECK-GI-NEXT: mov v0.b[2], w8
408-
; CHECK-GI-NEXT: fmov w8, s2
409-
; CHECK-GI-NEXT: mov v0.b[3], w8
410-
; CHECK-GI-NEXT: fmov w8, s3
411-
; CHECK-GI-NEXT: mov v0.b[4], w8
412-
; CHECK-GI-NEXT: fmov w8, s4
413-
; CHECK-GI-NEXT: mov v0.b[5], w8
414-
; CHECK-GI-NEXT: fmov w8, s5
415-
; CHECK-GI-NEXT: mov v0.b[6], w8
416-
; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
417-
; CHECK-GI-NEXT: ret
358+
; CHECK-LABEL: abs_v7i8:
359+
; CHECK: // %bb.0: // %entry
360+
; CHECK-NEXT: abs v0.8b, v0.8b
361+
; CHECK-NEXT: ret
418362
entry:
419363
%res = call <7 x i8> @llvm.abs.v7i8(<7 x i8> %a, i1 0)
420364
ret <7 x i8> %res
@@ -453,29 +397,10 @@ entry:
453397
declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)
454398

455399
define <7 x i16> @abs_v7i16(<7 x i16> %a){
456-
; CHECK-SD-LABEL: abs_v7i16:
457-
; CHECK-SD: // %bb.0: // %entry
458-
; CHECK-SD-NEXT: abs v0.8h, v0.8h
459-
; CHECK-SD-NEXT: ret
460-
;
461-
; CHECK-GI-LABEL: abs_v7i16:
462-
; CHECK-GI: // %bb.0: // %entry
463-
; CHECK-GI-NEXT: mov v1.h[0], v0.h[0]
464-
; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]
465-
; CHECK-GI-NEXT: mov v1.h[2], v0.h[2]
466-
; CHECK-GI-NEXT: mov v1.h[3], v0.h[3]
467-
; CHECK-GI-NEXT: mov v1.h[4], v0.h[4]
468-
; CHECK-GI-NEXT: mov v1.h[5], v0.h[5]
469-
; CHECK-GI-NEXT: mov v1.h[6], v0.h[6]
470-
; CHECK-GI-NEXT: abs v1.8h, v1.8h
471-
; CHECK-GI-NEXT: mov v0.h[0], v1.h[0]
472-
; CHECK-GI-NEXT: mov v0.h[1], v1.h[1]
473-
; CHECK-GI-NEXT: mov v0.h[2], v1.h[2]
474-
; CHECK-GI-NEXT: mov v0.h[3], v1.h[3]
475-
; CHECK-GI-NEXT: mov v0.h[4], v1.h[4]
476-
; CHECK-GI-NEXT: mov v0.h[5], v1.h[5]
477-
; CHECK-GI-NEXT: mov v0.h[6], v1.h[6]
478-
; CHECK-GI-NEXT: ret
400+
; CHECK-LABEL: abs_v7i16:
401+
; CHECK: // %bb.0: // %entry
402+
; CHECK-NEXT: abs v0.8h, v0.8h
403+
; CHECK-NEXT: ret
479404
entry:
480405
%res = call <7 x i16> @llvm.abs.v7i16(<7 x i16> %a, i1 0)
481406
ret <7 x i16> %res

‎llvm/test/CodeGen/AArch64/bitcast.ll‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -647,13 +647,7 @@ define <6 x i16> @bitcast_v3i32_v6i16(<3 x i32> %a, <3 x i32> %b){
647647
; CHECK-GI-NEXT: mov v3.s[1], v1.s[1]
648648
; CHECK-GI-NEXT: mov v2.s[2], v0.s[2]
649649
; CHECK-GI-NEXT: mov v3.s[2], v1.s[2]
650-
; CHECK-GI-NEXT: add v1.4s, v2.4s, v3.4s
651-
; CHECK-GI-NEXT: mov v0.h[0], v1.h[0]
652-
; CHECK-GI-NEXT: mov v0.h[1], v1.h[1]
653-
; CHECK-GI-NEXT: mov v0.h[2], v1.h[2]
654-
; CHECK-GI-NEXT: mov v0.h[3], v1.h[3]
655-
; CHECK-GI-NEXT: mov v0.h[4], v1.h[4]
656-
; CHECK-GI-NEXT: mov v0.h[5], v1.h[5]
650+
; CHECK-GI-NEXT: add v0.4s, v2.4s, v3.4s
657651
; CHECK-GI-NEXT: ret
658652
%c = add <3 x i32> %a, %b
659653
%d = bitcast <3 x i32> %c to <6 x i16>

‎llvm/test/CodeGen/AArch64/bswap.ll‎

Lines changed: 4 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -277,29 +277,10 @@ entry:
277277
declare <3 x i16> @llvm.bswap.v3i16(<3 x i16>)
278278

279279
define <7 x i16> @bswap_v7i16(<7 x i16> %a){
280-
; CHECK-SD-LABEL: bswap_v7i16:
281-
; CHECK-SD: // %bb.0: // %entry
282-
; CHECK-SD-NEXT: rev16 v0.16b, v0.16b
283-
; CHECK-SD-NEXT: ret
284-
;
285-
; CHECK-GI-LABEL: bswap_v7i16:
286-
; CHECK-GI: // %bb.0: // %entry
287-
; CHECK-GI-NEXT: mov v1.h[0], v0.h[0]
288-
; CHECK-GI-NEXT: mov v1.h[1], v0.h[1]
289-
; CHECK-GI-NEXT: mov v1.h[2], v0.h[2]
290-
; CHECK-GI-NEXT: mov v1.h[3], v0.h[3]
291-
; CHECK-GI-NEXT: mov v1.h[4], v0.h[4]
292-
; CHECK-GI-NEXT: mov v1.h[5], v0.h[5]
293-
; CHECK-GI-NEXT: mov v1.h[6], v0.h[6]
294-
; CHECK-GI-NEXT: rev16 v1.16b, v1.16b
295-
; CHECK-GI-NEXT: mov v0.h[0], v1.h[0]
296-
; CHECK-GI-NEXT: mov v0.h[1], v1.h[1]
297-
; CHECK-GI-NEXT: mov v0.h[2], v1.h[2]
298-
; CHECK-GI-NEXT: mov v0.h[3], v1.h[3]
299-
; CHECK-GI-NEXT: mov v0.h[4], v1.h[4]
300-
; CHECK-GI-NEXT: mov v0.h[5], v1.h[5]
301-
; CHECK-GI-NEXT: mov v0.h[6], v1.h[6]
302-
; CHECK-GI-NEXT: ret
280+
; CHECK-LABEL: bswap_v7i16:
281+
; CHECK: // %bb.0: // %entry
282+
; CHECK-NEXT: rev16 v0.16b, v0.16b
283+
; CHECK-NEXT: ret
303284
entry:
304285
%res = call <7 x i16> @llvm.bswap.v7i16(<7 x i16> %a)
305286
ret <7 x i16> %res

‎llvm/test/CodeGen/AArch64/fabs.ll‎

Lines changed: 3 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -174,41 +174,13 @@ define <7 x half> @fabs_v7f16(<7 x half> %a) {
174174
;
175175
; CHECK-GI-NOFP16-LABEL: fabs_v7f16:
176176
; CHECK-GI-NOFP16: // %bb.0: // %entry
177-
; CHECK-GI-NOFP16-NEXT: mov v1.h[0], v0.h[0]
178-
; CHECK-GI-NOFP16-NEXT: mov v1.h[1], v0.h[1]
179-
; CHECK-GI-NOFP16-NEXT: mov v1.h[2], v0.h[2]
180-
; CHECK-GI-NOFP16-NEXT: mov v1.h[3], v0.h[3]
181-
; CHECK-GI-NOFP16-NEXT: mov v1.h[4], v0.h[4]
182-
; CHECK-GI-NOFP16-NEXT: mov v1.h[5], v0.h[5]
183-
; CHECK-GI-NOFP16-NEXT: mov v1.h[6], v0.h[6]
184-
; CHECK-GI-NOFP16-NEXT: mvni v0.8h, #128, lsl #8
185-
; CHECK-GI-NOFP16-NEXT: and v1.16b, v1.16b, v0.16b
186-
; CHECK-GI-NOFP16-NEXT: mov v0.h[0], v1.h[0]
187-
; CHECK-GI-NOFP16-NEXT: mov v0.h[1], v1.h[1]
188-
; CHECK-GI-NOFP16-NEXT: mov v0.h[2], v1.h[2]
189-
; CHECK-GI-NOFP16-NEXT: mov v0.h[3], v1.h[3]
190-
; CHECK-GI-NOFP16-NEXT: mov v0.h[4], v1.h[4]
191-
; CHECK-GI-NOFP16-NEXT: mov v0.h[5], v1.h[5]
192-
; CHECK-GI-NOFP16-NEXT: mov v0.h[6], v1.h[6]
177+
; CHECK-GI-NOFP16-NEXT: mvni v1.8h, #128, lsl #8
178+
; CHECK-GI-NOFP16-NEXT: and v0.16b, v0.16b, v1.16b
193179
; CHECK-GI-NOFP16-NEXT: ret
194180
;
195181
; CHECK-GI-FP16-LABEL: fabs_v7f16:
196182
; CHECK-GI-FP16: // %bb.0: // %entry
197-
; CHECK-GI-FP16-NEXT: mov v1.h[0], v0.h[0]
198-
; CHECK-GI-FP16-NEXT: mov v1.h[1], v0.h[1]
199-
; CHECK-GI-FP16-NEXT: mov v1.h[2], v0.h[2]
200-
; CHECK-GI-FP16-NEXT: mov v1.h[3], v0.h[3]
201-
; CHECK-GI-FP16-NEXT: mov v1.h[4], v0.h[4]
202-
; CHECK-GI-FP16-NEXT: mov v1.h[5], v0.h[5]
203-
; CHECK-GI-FP16-NEXT: mov v1.h[6], v0.h[6]
204-
; CHECK-GI-FP16-NEXT: fabs v1.8h, v1.8h
205-
; CHECK-GI-FP16-NEXT: mov v0.h[0], v1.h[0]
206-
; CHECK-GI-FP16-NEXT: mov v0.h[1], v1.h[1]
207-
; CHECK-GI-FP16-NEXT: mov v0.h[2], v1.h[2]
208-
; CHECK-GI-FP16-NEXT: mov v0.h[3], v1.h[3]
209-
; CHECK-GI-FP16-NEXT: mov v0.h[4], v1.h[4]
210-
; CHECK-GI-FP16-NEXT: mov v0.h[5], v1.h[5]
211-
; CHECK-GI-FP16-NEXT: mov v0.h[6], v1.h[6]
183+
; CHECK-GI-FP16-NEXT: fabs v0.8h, v0.8h
212184
; CHECK-GI-FP16-NEXT: ret
213185
entry:
214186
%c = call <7 x half> @llvm.fabs.v7f16(<7 x half> %a)

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