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[LLVM] [NFC] Add more tests for uniformity analysis
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‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/branch-after-join.ll‎

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;
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; RUN: opt -mtriple amdgcn-- -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s
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;
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;
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; Entry (div.cond)
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; / \
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; B0 B3
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; | |
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; B1 B4
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; | |
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; \ /
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; B5 (phi: divergent)
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; |
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; B6 (div.uni)
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; / \
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; B7 B9
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; | |
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; B8 B10
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; | |
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; \ /
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; B11 (phi: uniform)
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; CHECK-LABEL: 'test_ctrl_divergence':
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; CHECK-LABEL: BLOCK Entry
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; CHECK: DIVERGENT: %div.cond = icmp eq i32 %tid, 0
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; CHECK: DIVERGENT: br i1 %div.cond, label %B3, label %B0
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;
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; CHECK-LABEL: BLOCK B5
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; CHECK: DIVERGENT: %div_a = phi i32 [ %a0, %B1 ], [ %a1, %B4 ]
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; CHECK: DIVERGENT: %div_b = phi i32 [ %b0, %B1 ], [ %b1, %B4 ]
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;
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; CHECK-LABEL: BLOCK B6
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; CHECK-NOT: DIVERGENT: %uni.cond = icmp
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; CHECK-NOT: DIVERGENT: br i1 %div.cond
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;
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; CHECK-LABEL: BLOCK B11
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; CHECK-NOT: DIVERGENT: %div_d = phi i32
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define amdgpu_kernel void @test_ctrl_divergence(i32 %a, i32 %b, i32 %c, i32 %d) {
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Entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%div.cond = icmp eq i32 %tid, 0
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br i1 %div.cond, label %B3, label %B0 ; divergent branch
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B0:
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%a0 = add i32 %a, 1
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br label %B1
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B1:
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%b0 = add i32 %b, 2
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br label %B5
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B3:
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%a1 = add i32 %a, 10
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br label %B4
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B4:
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%b1 = add i32 %b, 20
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br label %B5
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B5:
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%div_a = phi i32 [%a0, %B1], [%a1, %B4]
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%div_b = phi i32 [%b0, %B1], [%b1, %B4]
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br label %B6
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B6:
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%uni.cond = icmp eq i32 %c, 0
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br i1 %uni.cond, label %B7, label %B9
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B7:
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%d1 = add i32 %d, 1
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br label %B8
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B8:
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br label %B11
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B9:
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%d2 = add i32 %d, 3
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br label %B10
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B10:
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br label %B11
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B11:
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%div_d = phi i32 [%d1, %B8], [%d2, %B10]
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = {nounwind readnone }

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/irreducible/hidden-post-dom.ll‎

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; RUN: opt %s -mtriple amdgcn-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s
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define amdgpu_kernel void @cycle_inner_ipd(i32 %n, i32 %a, i32 %b) #0 {
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;
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; entry
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; / \
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; E2<------E1
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; | \ ^^
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; | \ / |
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; | v/ |
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; | A |
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; | / |
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; | / |
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; vv |
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; B------->C
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; |
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; X
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;
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;
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; CHECK-LABEL: BLOCK entry
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; CHECK: DIVERGENT: %tid = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK: DIVERGENT: %div.cond = icmp slt i32 %tid, 0
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; CHECK: END BLOCK
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;
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; CHECK-LABEL: BLOCK B
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; CHECK: DIVERGENT: %div.merge = phi i32 [ 0, %A ], [ %b, %E2 ]
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; CHECK: END BLOCK
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%div.cond = icmp slt i32 %tid, 0
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%uni.cond = icmp slt i32 %a, 0
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%uni.cond1 = icmp slt i32 %a, 2
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%uni.cond2 = icmp slt i32 %a, 10
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br i1 %uni.cond, label %E2, label %E1
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E1:
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br label %E2
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E2:
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br i1 %uni.cond1, label %A, label %B
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A:
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br i1 %div.cond, label %E1, label %B
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B:
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%div.merge = phi i32 [ 0, %A ], [ %b, %E2 ]
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br label %C
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C:
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br i1 %uni.cond2, label %E1, label %X
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X:
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ret void
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}

‎llvm/test/Analysis/UniformityAnalysis/AMDGPU/unstructured-branch.ll‎

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; RUN: opt -mtriple amdgcn-- -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s
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; Alpha (div.uni)
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; | \
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; Entry \
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; (div.cond)\
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; / \ \
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; B0 B3 |
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; | | |
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; B1 B4<-+
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; | |
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; B2 B5
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; / | |
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; / | B501
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; / | |
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; B201->B202 B502
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; \ /
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; B6 (phi: divergent)
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;
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;
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; CHECK-LABEL: 'test_ctrl_divergence':
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; CHECK-LABEL: BLOCK Entry
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; CHECK: DIVERGENT: %div.cond = icmp eq i32 %tid, 0
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; CHECK: DIVERGENT: br i1 %div.cond, label %B3, label %B0
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;
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; CHECK-LABEL: BLOCK B6
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; CHECK: DIVERGENT: %div_a = phi i32 [ %a0, %B202 ], [ %a1, %B502 ]
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; CHECK: DIVERGENT: %div_b = phi i32 [ %b0, %B202 ], [ %b1, %B502 ]
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; CHECK: DIVERGENT: %div_c = phi i32 [ %c0, %B202 ], [ %c1, %B502 ]
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define amdgpu_kernel void @test_ctrl_divergence(i32 %a, i32 %b, i32 %c, i32 %d) {
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Alpha:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%div.uni = icmp eq i32 %a, 0
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br i1 %div.uni, label %Entry, label %B4
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Entry:
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%div.cond = icmp eq i32 %tid, 0
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br i1 %div.cond, label %B3, label %B0 ; divergent branch
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B0:
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br label %B1
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B1:
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br label %B2
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B2:
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%a0 = add i32 %a, 1
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%b0 = add i32 %b, 2
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%c0 = add i32 %c, 3
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br i1 %div.uni, label %B201, label %B202
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B201:
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br label %B202
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B202:
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br label %B6
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B3:
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br label %B4
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B4:
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%a1 = add i32 %a, 10
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%b1 = add i32 %b, 20
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%c1 = add i32 %c, 30
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br i1 %div.uni, label %B5, label %B501
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B5:
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br label %B501
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B501:
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br label %B502
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B502:
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br label %B6
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B6:
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%div_a = phi i32 [%a0, %B202], [%a1, %B502]
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%div_b = phi i32 [%b0, %B202], [%b1, %B502]
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%div_c = phi i32 [%c0, %B202], [%c1, %B502]
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = {nounwind readnone }

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