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[Associativity]: Make FMul associative operator
Change-Id: I8231774b6fa7c446d221a4e32098788af32072bb
1 parent b90ea5c commit 55d5f62

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9 files changed

+39
-50
lines changed

9 files changed

+39
-50
lines changed

‎llvm/include/llvm/IR/Instruction.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -696,8 +696,8 @@ class Instruction : public User,
696696
///
697697
bool isAssociative() const LLVM_READONLY;
698698
static bool isAssociative(unsigned Opcode) {
699-
return Opcode == And || Opcode == Or || Opcode == Xor ||
700-
Opcode == Add || Opcode == Mul;
699+
return Opcode == And || Opcode == Or || Opcode == Xor || Opcode == Add ||
700+
Opcode == Mul || Opcode == FMul;
701701
}
702702

703703
/// Return true if the instruction is commutative:

‎llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -139,11 +139,14 @@ define void @main(i1 %arg) #0 {
139139
; CHECK-NEXT: v_readlane_b32 s38, v7, 2
140140
; CHECK-NEXT: v_readlane_b32 s39, v7, 3
141141
; CHECK-NEXT: v_readlane_b32 s40, v7, 4
142-
; CHECK-NEXT: image_sample_lz v3, v[1:2], s[44:51], s[20:23] dmask:0x1
143-
; CHECK-NEXT: v_mov_b32_e32 v2, 0
142+
; CHECK-NEXT: image_sample_lz v2, v[1:2], s[44:51], s[20:23] dmask:0x1
144143
; CHECK-NEXT: v_readlane_b32 s41, v7, 5
145144
; CHECK-NEXT: v_readlane_b32 s42, v7, 6
146145
; CHECK-NEXT: v_readlane_b32 s43, v7, 7
146+
; CHECK-NEXT: s_waitcnt vmcnt(0)
147+
; CHECK-NEXT: v_mul_f32_e32 v3, v0, v2
148+
; CHECK-NEXT: v_mov_b32_e32 v2, 0
149+
; CHECK-NEXT: ; implicit-def: $vgpr0
147150
; CHECK-NEXT: .LBB0_2: ; %bb50
148151
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
149152
; CHECK-NEXT: v_readlane_b32 s36, v7, 32
@@ -162,7 +165,6 @@ define void @main(i1 %arg) #0 {
162165
; CHECK-NEXT: image_sample_lz v1, v[1:2], s[12:19], s[20:23] dmask:0x1
163166
; CHECK-NEXT: s_waitcnt vmcnt(0)
164167
; CHECK-NEXT: v_sub_f32_e32 v1, v1, v4
165-
; CHECK-NEXT: v_mul_f32_e32 v1, v1, v0
166168
; CHECK-NEXT: v_mul_f32_e32 v1, v1, v3
167169
; CHECK-NEXT: s_mov_b64 vcc, vcc
168170
; CHECK-NEXT: s_cbranch_vccnz .LBB0_2

‎llvm/test/Transforms/InstCombine/2006-10-26-VectorReassoc.ll‎

Lines changed: 4 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,8 @@
44
; Verify this doesn't fold when no fast-math-flags are specified
55
define <4 x float> @test_fmul(<4 x float> %V) {
66
; CHECK-LABEL: @test_fmul(
7-
; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x float> [[V:%.*]], <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
8-
; CHECK-NEXT: [[TMP2:%.*]] = fmul <4 x float> [[TMP1]], <float 1.000000e+00, float 2.000000e+05, float -3.000000e+00, float 4.000000e+00>
9-
; CHECK-NEXT: ret <4 x float> [[TMP2]]
7+
; CHECK-NEXT: [[TMP1:%.*]] = fmul <4 x float> [[V:%.*]], <float 1.000000e+00, float 4.000000e+05, float -9.000000e+00, float 1.600000e+01>
8+
; CHECK-NEXT: ret <4 x float> [[TMP1]]
109
%Y = fmul <4 x float> %V, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >
1110
%Z = fmul <4 x float> %Y, < float 1.000000e+00, float 2.000000e+05, float -3.000000e+00, float 4.000000e+00 >
1211
ret <4 x float> %Z
@@ -35,12 +34,10 @@ define <4 x float> @test_fmul_reassoc_nsz(<4 x float> %V) {
3534
}
3635

3736
; (V * C1) * C2 => V * (C1 * C2)
38-
; TODO: This doesn't require 'nsz'. It should fold to V * { 1.0, 4.0e+05, -9.0, 16.0 }
3937
define <4 x float> @test_fmul_reassoc(<4 x float> %V) {
4038
; CHECK-LABEL: @test_fmul_reassoc(
41-
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc <4 x float> [[V:%.*]], <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>
42-
; CHECK-NEXT: [[TMP2:%.*]] = fmul reassoc <4 x float> [[TMP1]], <float 1.000000e+00, float 2.000000e+05, float -3.000000e+00, float 4.000000e+00>
43-
; CHECK-NEXT: ret <4 x float> [[TMP2]]
39+
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc <4 x float> [[V]], <float 1.000000e+00, float 4.000000e+05, float -9.000000e+00, float 1.600000e+01>
40+
; CHECK-NEXT: ret <4 x float> [[TMP1]]
4441
%Y = fmul reassoc <4 x float> %V, < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >
4542
%Z = fmul reassoc <4 x float> %Y, < float 1.000000e+00, float 2.000000e+05, float -3.000000e+00, float 4.000000e+00 >
4643
ret <4 x float> %Z

‎llvm/test/Transforms/InstCombine/fast-math.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,7 @@ define float @fold(float %a) {
1717
; fixed FP mode.
1818
define float @notfold(float %a) {
1919
; CHECK-LABEL: @notfold(
20-
; CHECK-NEXT: [[MUL:%.*]] = fmul fast float [[A:%.*]], 0x3FF3333340000000
21-
; CHECK-NEXT: [[MUL1:%.*]] = fmul float [[MUL]], 0x4002666660000000
20+
; CHECK-NEXT: [[MUL1:%.*]] = fmul float [[A:%.*]], 0x4006147AE0000000
2221
; CHECK-NEXT: ret float [[MUL1]]
2322
;
2423
%mul = fmul fast float %a, 0x3FF3333340000000

‎llvm/test/Transforms/InstCombine/fdiv.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -524,8 +524,7 @@ define <2 x float> @div_constant_dividend2_reassoc_only(<2 x float> %x) {
524524

525525
define <2 x float> @div_constant_dividend3(<2 x float> %x) {
526526
; CHECK-LABEL: @div_constant_dividend3(
527-
; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc arcp <2 x float> [[X:%.*]], <float 1.500000e+01, float -7.000000e+00>
528-
; CHECK-NEXT: [[T2:%.*]] = fmul reassoc arcp <2 x float> [[TMP1]], <float 0x3FD5555560000000, float 0x3FC24924A0000000>
527+
; CHECK-NEXT: [[T2:%.*]] = fmul reassoc arcp <2 x float> [[X:%.*]], <float 5.000000e+00, float -1.000000e+00>
529528
; CHECK-NEXT: ret <2 x float> [[T2]]
530529
;
531530
%t1 = fdiv <2 x float> <float 3.0e0, float 7.0e0>, %x

‎llvm/test/Transforms/LICM/hoist-binop.ll‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -562,12 +562,13 @@ loop:
562562
define void @fmul_noassoc(float %c1, float %c2) {
563563
; CHECK-LABEL: @fmul_noassoc(
564564
; CHECK-NEXT: entry:
565+
; CHECK-NEXT: [[INVARIANT_OP:%.*]] = fmul nsz float [[C1:%.*]], [[C2:%.*]]
565566
; CHECK-NEXT: br label [[LOOP:%.*]]
566567
; CHECK: loop:
567568
; CHECK-NEXT: [[INDEX:%.*]] = phi float [ 0.000000e+00, [[ENTRY:%.*]] ], [ [[INDEX_NEXT:%.*]], [[LOOP]] ]
568-
; CHECK-NEXT: [[STEP_ADD:%.*]] = fmul reassoc nsz float [[INDEX]], [[C1:%.*]]
569+
; CHECK-NEXT: [[STEP_ADD:%.*]] = fmul reassoc nsz float [[INDEX]], [[C1]]
569570
; CHECK-NEXT: call void @use(float [[STEP_ADD]])
570-
; CHECK-NEXT: [[INDEX_NEXT]] = fmul nsz float [[STEP_ADD]], [[C2:%.*]]
571+
; CHECK-NEXT: [[INDEX_NEXT]] = fmul nsz float [[INDEX]], [[INVARIANT_OP]]
571572
; CHECK-NEXT: br label [[LOOP]]
572573
;
573574
entry:

‎llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,14 @@ define void @test(double %i) {
1111
; CHECK-NEXT: [[TMP3:%.*]] = fsub <2 x double> zeroinitializer, [[TMP2]]
1212
; CHECK-NEXT: [[I75:%.*]] = fsub double 0.000000e+00, [[I]]
1313
; CHECK-NEXT: [[TMP5:%.*]] = fsub <2 x double> [[TMP0]], zeroinitializer
14-
; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> [[TMP5]], <4 x i32> <i32 poison, i32 0, i32 2, i32 poison>
15-
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP5]], <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
16-
; CHECK-NEXT: [[TMP28:%.*]] = shufflevector <4 x double> [[TMP6]], <4 x double> [[TMP7]], <8 x i32> <i32 poison, i32 poison, i32 0, i32 poison, i32 poison, i32 5, i32 6, i32 poison>
17-
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x double> [[TMP28]], <8 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double poison, double 0.000000e+00, double poison, double poison, double poison>, <8 x i32> <i32 8, i32 9, i32 2, i32 poison, i32 12, i32 5, i32 6, i32 poison>
18-
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <8 x double> [[TMP8]], double [[I75]], i32 3
19-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x double> [[TMP9]], <8 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 3>
20-
; CHECK-NEXT: [[TMP11:%.*]] = fmul <8 x double> zeroinitializer, [[TMP10]]
14+
; CHECK-NEXT: [[TMP28:%.*]] = insertelement <2 x double> [[TMP5]], double [[I75]], i32 1
15+
; CHECK-NEXT: [[TMP6:%.*]] = fmul <2 x double> zeroinitializer, [[TMP28]]
16+
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x double> [[TMP1]], i32 0
17+
; CHECK-NEXT: [[I87:%.*]] = fmul double 0.000000e+00, [[TMP7]]
18+
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x double> [[TMP6]], <2 x double> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
19+
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x double> <double 0.000000e+00, double 0.000000e+00, double poison, double poison, double 0.000000e+00, double poison, double poison, double poison>, <8 x double> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 8, i32 9, i32 4, i32 poison, i32 poison, i32 poison>
20+
; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x double> [[TMP9]], double [[I87]], i32 5
21+
; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <8 x double> [[TMP10]], <8 x double> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 2, i32 3>
2122
; CHECK-NEXT: [[TMP12:%.*]] = fadd <8 x double> zeroinitializer, [[TMP11]]
2223
; CHECK-NEXT: [[TMP13:%.*]] = fadd <8 x double> [[TMP12]], zeroinitializer
2324
; CHECK-NEXT: [[TMP14:%.*]] = fcmp ult <8 x double> [[TMP13]], zeroinitializer

‎llvm/test/Transforms/SLPVectorizer/buildvector-nodes-dependency.ll‎

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -8,29 +8,21 @@ define double @test() {
88
; CHECK-NEXT: [[TMP0:%.*]] = load double, ptr null, align 8
99
; CHECK-NEXT: br label [[COND_TRUE:%.*]]
1010
; CHECK: cond.true:
11-
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> <double 0.000000e+00, double poison>, double [[TMP0]], i32 1
11+
; CHECK-NEXT: [[MUL13:%.*]] = fmul double [[TMP0]], 0.000000e+00
12+
; CHECK-NEXT: [[OP_RDX4:%.*]] = fmul double 0.000000e+00, [[TMP0]]
13+
; CHECK-NEXT: [[ADD17:%.*]] = fadd double [[MUL13]], [[OP_RDX4]]
14+
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[TMP0]], i32 0
15+
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> poison, <2 x i32> zeroinitializer
1216
; CHECK-NEXT: [[TMP2:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
13-
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
14-
; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[TMP3]], zeroinitializer
15-
; CHECK-NEXT: [[TMP5:%.*]] = fmul <2 x double> [[TMP3]], zeroinitializer
16-
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x double> [[TMP2]], <2 x double> [[TMP1]], <2 x i32> <i32 0, i32 3>
17-
; CHECK-NEXT: [[TMP7:%.*]] = fmul <2 x double> [[TMP6]], zeroinitializer
18-
; CHECK-NEXT: [[TMP8:%.*]] = fsub <2 x double> [[TMP7]], zeroinitializer
19-
; CHECK-NEXT: [[TMP9:%.*]] = fmul <2 x double> [[TMP7]], zeroinitializer
20-
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP8]], <2 x double> [[TMP9]], <2 x i32> <i32 0, i32 3>
21-
; CHECK-NEXT: [[TMP11:%.*]] = fadd <2 x double> zeroinitializer, [[TMP10]]
22-
; CHECK-NEXT: [[TMP12:%.*]] = fmul <2 x double> zeroinitializer, [[TMP10]]
23-
; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x double> [[TMP11]], <2 x double> [[TMP12]], <2 x i32> <i32 0, i32 3>
24-
; CHECK-NEXT: [[TMP14:%.*]] = fsub <2 x double> [[TMP13]], [[TMP2]]
25-
; CHECK-NEXT: [[TMP15:%.*]] = fadd <2 x double> [[TMP13]], [[TMP2]]
26-
; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <2 x double> [[TMP14]], <2 x double> [[TMP15]], <2 x i32> <i32 0, i32 3>
17+
; CHECK-NEXT: [[TMP23:%.*]] = fmul <2 x double> zeroinitializer, [[TMP1]]
18+
; CHECK-NEXT: [[SUB:%.*]] = fsub double 0.000000e+00, 0.000000e+00
19+
; CHECK-NEXT: [[ADD:%.*]] = fadd double 0.000000e+00, [[SUB]]
20+
; CHECK-NEXT: [[SUB2:%.*]] = fsub double [[ADD]], 0.000000e+00
21+
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> poison, double [[SUB2]], i32 0
22+
; CHECK-NEXT: [[TMP16:%.*]] = insertelement <2 x double> [[TMP5]], double [[ADD17]], i32 1
2723
; CHECK-NEXT: [[TMP17:%.*]] = fsub <2 x double> [[TMP16]], zeroinitializer
28-
; CHECK-NEXT: [[TMP18:%.*]] = fmul <2 x double> [[TMP4]], zeroinitializer
29-
; CHECK-NEXT: [[TMP19:%.*]] = fmul <2 x double> zeroinitializer, [[TMP18]]
30-
; CHECK-NEXT: [[TMP20:%.*]] = fadd <2 x double> [[TMP19]], [[TMP17]]
24+
; CHECK-NEXT: [[TMP20:%.*]] = fadd <2 x double> [[TMP2]], [[TMP17]]
3125
; CHECK-NEXT: [[TMP21:%.*]] = fsub <2 x double> [[TMP20]], zeroinitializer
32-
; CHECK-NEXT: [[TMP22:%.*]] = fmul <2 x double> [[TMP5]], zeroinitializer
33-
; CHECK-NEXT: [[TMP23:%.*]] = fmul <2 x double> zeroinitializer, [[TMP22]]
3426
; CHECK-NEXT: [[TMP24:%.*]] = fadd <2 x double> [[TMP23]], [[TMP21]]
3527
; CHECK-NEXT: [[TMP25:%.*]] = extractelement <2 x double> [[TMP24]], i32 0
3628
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <2 x double> [[TMP24]], i32 1

‎llvm/test/Transforms/SLPVectorizer/reschedule.ll‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8,19 +8,17 @@ declare void @use(double, double)
88
define void @test() {
99
; CHECK-LABEL: @test(
1010
; CHECK-NEXT: for.body602:
11-
; CHECK-NEXT: [[MUL701:%.*]] = fmul double 0.000000e+00, 0.000000e+00
12-
; CHECK-NEXT: [[MUL703:%.*]] = fmul double 0.000000e+00, 0.000000e+00
13-
; CHECK-NEXT: [[I4:%.*]] = call double @llvm.fmuladd.f64(double [[MUL701]], double 0.000000e+00, double [[MUL703]])
11+
; CHECK-NEXT: [[I4:%.*]] = call double @llvm.fmuladd.f64(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00)
1412
; CHECK-NEXT: store double [[I4]], ptr null, align 8
1513
; CHECK-NEXT: [[I5:%.*]] = load double, ptr null, align 8
1614
; CHECK-NEXT: [[I6:%.*]] = load double, ptr null, align 8
1715
; CHECK-NEXT: [[MUL746:%.*]] = fmul double 0.000000e+00, [[I6]]
1816
; CHECK-NEXT: [[MUL747:%.*]] = fmul double 0.000000e+00, [[I5]]
1917
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x double> poison, double [[MUL746]], i32 0
20-
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[MUL701]], i32 1
18+
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double 0.000000e+00, i32 1
2119
; CHECK-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, <2 x double> [[TMP1]])
2220
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <2 x double> poison, double [[MUL747]], i32 0
23-
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double [[MUL703]], i32 1
21+
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <2 x double> [[TMP3]], double 0.000000e+00, i32 1
2422
; CHECK-NEXT: [[TMP5:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP2]], <2 x double> zeroinitializer, <2 x double> [[TMP4]])
2523
; CHECK-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP5]], <2 x double> zeroinitializer, <2 x double> zeroinitializer)
2624
; CHECK-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> zeroinitializer, <2 x double> [[TMP6]], <2 x double> zeroinitializer)

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