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[DAG] Added test case for zext rotate
1 parent 7d3b32c commit 55f06ae

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2 files changed

+35
-4
lines changed

2 files changed

+35
-4
lines changed

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9846,7 +9846,7 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
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98479847
// It is a simple combine.
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if (!NeedsBswap)
9849-
return NewLoad;
9849+
return NewLoad;
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// It is a BSWAP combine.
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SDValue ShiftedLoad =
@@ -9864,7 +9864,7 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
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// Make sure we can rotate
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if (LegalOperations && !TLI.isOperationLegal(ISD::ROTR, VT))
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return SDValue();
9867-
9867+
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auto *FirstLoad = cast<LoadSDNode>(FirstByteProvider->Src.value());
98699869
if (MemoryByteOffset(*FirstByteProvider) != 0)
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return SDValue();
@@ -9890,9 +9890,9 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
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DAG.getNode(ISD::ROTR, SDLoc(N), MemVT, NewLoad,
98919891
DAG.getConstant(*RotateAmt, SDLoc(N), ShiftAmountTy));
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9893-
if (NeedsZext)
9893+
if (NeedsZext)
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return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Rotated);
9895-
9895+
98969896
return Rotated;
98979897
}
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llvm/test/CodeGen/X86/load-combine.ll

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1331,3 +1331,34 @@ define i64 @test_load_bswap_to_rotate(ptr %p) {
13311331
%or = or disjoint i64 %shl, %conv2
13321332
ret i64 %or
13331333
}
1334+
1335+
define i64 @test_load_rotate_zext(ptr %p) {
1336+
; CHECK64-LABEL: test_load_rotate_zext:
1337+
; CHECK64: # %bb.0:
1338+
; CHECK64-NEXT: movl (%rdi), %eax
1339+
; CHECK64-NEXT: rorl $8, %eax
1340+
; CHECK64-NEXT: retq
1341+
%p1 = getelementptr inbounds i8, ptr %p, i64 1
1342+
%l1 = load i8, ptr %p1, align 1
1343+
%e1 = zext i8 %l1 to i64
1344+
1345+
%p2 = getelementptr inbounds i8, ptr %p, i64 2
1346+
%l2 = load i8, ptr %p2, align 1
1347+
%e2 = zext i8 %l2 to i64
1348+
%s2 = shl i64 %e2, 8
1349+
1350+
%p3 = getelementptr inbounds i8, ptr %p, i64 3
1351+
%l3 = load i8, ptr %p3, align 1
1352+
%e3 = zext i8 %l3 to i64
1353+
%s3 = shl i64 %e3, 16
1354+
1355+
%p0 = getelementptr inbounds i8, ptr %p, i64 0
1356+
%l0 = load i8, ptr %p0, align 1
1357+
%e0 = zext i8 %l0 to i64
1358+
%s0 = shl i64 %e0, 24
1359+
1360+
%or1 = or i64 %e1, %s2
1361+
%or2 = or i64 %or1, %s3
1362+
%or3 = or i64 %or2, %s0
1363+
ret i64 %or3
1364+
}

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