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[InstCombine] Optimize sub(sext(add(x,y)),sext(add(x,z))).
This pattern can be often met in Flang generated LLVM IR, for example, for the counts of the loops generated for array expressions like: `a(x:x+y)` or `a(x+z:x+z)` or their variations. In order to compute the loop count, Flang needs to subtract the lower bound of the array slice from the upper bound of the array slice. To avoid the sign wraps, it sign extends the original values (that may be of any user data type) to `i64`. This peephole is really helpful in CPU2017/548.exchange2, where we have multiple following statements like this: ``` block(row+1:row+2, 7:9, i7) = block(row+1:row+2, 7:9, i7) - 10 ``` While this is just a 2x3 iterations loop nest, LLVM cannot figure it out, ending up vectorizing the inner loop really hard (with a vector epilog and scalar remainder). This, in turn, causes problems for LSR that ends up creating too many loop-carried values in the loop containing the above statement, which are then causing too many spills/reloads. Alive2: https://alive2.llvm.org/ce/z/gLgfYX Related to #143219.
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‎llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp‎

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2807,6 +2807,62 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
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if (Instruction *Res = foldBinOpOfSelectAndCastOfSelectCondition(I))
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return Res;
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// (sub[ nsw][ nuw] (sext (add nsw (X, Y)), sext (X))) --> (sext (Y))
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{
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Value *Add0;
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if (match(Op0, m_SExt(m_Value(Add0))) &&
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match(Add0, m_Add(m_Value(X), m_Value(Y))) &&
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match(Op1, m_SExt(m_Specific(X)))) {
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auto *OBO0 = cast<OverflowingBinaryOperator>(Add0);
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if (OBO0->hasNoSignedWrap()) {
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// Non-constant Y requires new SExt.
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unsigned numOfNewInstrs = !isa<Constant>(Y) ? 1 : 0;
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// Check if we can trade some of the old instructions for the new ones.
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unsigned numOfDeadInstrs = 0;
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numOfDeadInstrs += Op0->hasOneUse() ? 1 : 0;
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numOfDeadInstrs += Op1->hasOneUse() ? 1 : 0;
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numOfDeadInstrs += Add0->hasOneUse() ? 1 : 0;
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if (numOfDeadInstrs >= numOfNewInstrs) {
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Value *SExtY = Builder.CreateSExt(Y, I.getType());
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return replaceInstUsesWith(I, SExtY);
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}
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}
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}
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}
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// (sub[ nsw] (sext (add nsw (X, Y)), sext (add nsw (X, Z)))) -->
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// --> (sub[ nsw] (sext (Y), sext(Z)))
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{
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Value *Z, *Add0, *Add1;
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if (match(Op0, m_SExt(m_Value(Add0))) &&
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match(Add0, m_Add(m_Value(X), m_Value(Y))) &&
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match(Op1, m_SExt(m_Value(Add1))) &&
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match(Add1, m_Add(m_Specific(X), m_Value(Z)))) {
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auto *OBO0 = cast<OverflowingBinaryOperator>(Add0);
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auto *OBO1 = cast<OverflowingBinaryOperator>(Add1);
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if (OBO0->hasNoSignedWrap() && OBO1->hasNoSignedWrap()) {
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unsigned numOfNewInstrs = 0;
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// Non-constant Y, Z require new SExt.
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numOfNewInstrs += !isa<Constant>(Y) ? 1 : 0;
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numOfNewInstrs += !isa<Constant>(Z) ? 1 : 0;
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// Check if we can trade some of the old instructions for the new ones.
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unsigned numOfDeadInstrs = 0;
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numOfDeadInstrs += Op0->hasOneUse() ? 1 : 0;
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numOfDeadInstrs += Op1->hasOneUse() ? 1 : 0;
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numOfDeadInstrs += Add0->hasOneUse() ? 1 : 0;
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numOfDeadInstrs += Add1->hasOneUse() ? 1 : 0;
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if (numOfDeadInstrs >= numOfNewInstrs) {
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Value *SExtY = Builder.CreateSExt(Y, I.getType());
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Value *SExtZ = Builder.CreateSExt(Z, I.getType());
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Value *Sub = Builder.CreateSub(SExtY, SExtZ, "",
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/* HasNUW */ false,
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/* HasNSW */ I.hasNoSignedWrap());
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return replaceInstUsesWith(I, Sub);
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}
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}
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}
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}
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return TryToNarrowDeduceFlags();
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}
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‎llvm/test/Transforms/InstCombine/sub-sext-add.ll‎

Lines changed: 89 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,89 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i64 @src_2add_2sext_sub(i32 %x, i32 %y, i32 %z) {
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; CHECK-LABEL: define i64 @src_2add_2sext_sub(
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; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) {
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; CHECK-NEXT: [[SEXT1:%.*]] = sext i32 [[Y]] to i64
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; CHECK-NEXT: [[SEXT2:%.*]] = sext i32 [[Z]] to i64
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[SEXT1]], [[SEXT2]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%add1 = add nsw i32 %x, %y
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%add2 = add nsw i32 %x, %z
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%sext1 = sext i32 %add1 to i64
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%sext2 = sext i32 %add2 to i64
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%sub = sub i64 %sext1, %sext2
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ret i64 %sub
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}
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20+
define i64 @src_2add_2sext_sub_nsw(i32 %x, i32 %y, i32 %z) {
21+
; CHECK-LABEL: define i64 @src_2add_2sext_sub_nsw(
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; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) {
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; CHECK-NEXT: [[SEXT1:%.*]] = sext i32 [[Y]] to i64
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; CHECK-NEXT: [[SEXT2:%.*]] = sext i32 [[Z]] to i64
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[SEXT1]], [[SEXT2]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
28+
%add1 = add nsw i32 %x, %y
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%add2 = add nsw i32 %x, %z
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%sext1 = sext i32 %add1 to i64
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%sext2 = sext i32 %add2 to i64
32+
%sub = sub nsw i64 %sext1, %sext2
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ret i64 %sub
34+
}
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36+
define i64 @src_2add_2sext_sub_nuw(i32 %x, i32 %y, i32 %z) {
37+
; CHECK-LABEL: define i64 @src_2add_2sext_sub_nuw(
38+
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]], i32 [[Z:%.*]]) {
39+
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[Y]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[Z]] to i64
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; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[TMP1]], [[TMP2]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%add1 = add nsw i32 %x, %y
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%add2 = add nsw i32 %x, %z
46+
%sext1 = sext i32 %add1 to i64
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%sext2 = sext i32 %add2 to i64
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%sub = sub nuw i64 %sext1, %sext2
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ret i64 %sub
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}
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define i64 @src_x_add_2sext_sub(i32 %x, i32 %y) {
53+
; CHECK-LABEL: define i64 @src_x_add_2sext_sub(
54+
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
55+
; CHECK-NEXT: [[SUB:%.*]] = sext i32 [[Y]] to i64
56+
; CHECK-NEXT: ret i64 [[SUB]]
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;
58+
%add1 = add nsw i32 %x, %y
59+
%sext1 = sext i32 %add1 to i64
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%sext2 = sext i32 %x to i64
61+
%sub = sub i64 %sext1, %sext2
62+
ret i64 %sub
63+
}
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65+
define i64 @src_x_add_2sext_sub_nsw(i32 %x, i32 %y) {
66+
; CHECK-LABEL: define i64 @src_x_add_2sext_sub_nsw(
67+
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
68+
; CHECK-NEXT: [[SUB:%.*]] = sext i32 [[Y]] to i64
69+
; CHECK-NEXT: ret i64 [[SUB]]
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;
71+
%add1 = add nsw i32 %x, %y
72+
%sext1 = sext i32 %add1 to i64
73+
%sext2 = sext i32 %x to i64
74+
%sub = sub nsw i64 %sext1, %sext2
75+
ret i64 %sub
76+
}
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78+
define i64 @src_x_add_2sext_sub_nuw(i32 %x, i32 %y) {
79+
; CHECK-LABEL: define i64 @src_x_add_2sext_sub_nuw(
80+
; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) {
81+
; CHECK-NEXT: [[SUB:%.*]] = sext i32 [[Y]] to i64
82+
; CHECK-NEXT: ret i64 [[SUB]]
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;
84+
%add1 = add nsw i32 %x, %y
85+
%sext1 = sext i32 %add1 to i64
86+
%sext2 = sext i32 %x to i64
87+
%sub = sub nuw i64 %sext1, %sext2
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ret i64 %sub
89+
}

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