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fixup: address comments
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+22
-59
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7 files changed

+22
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‎llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp‎

Lines changed: 11 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -6,25 +6,18 @@
66
//
77
//===----------------------------------------------------------------------===//
88
//
9-
// This pass implements two key optimizations for RISC-V memory accesses:
10-
// 1. Load/Store Pairing: It identifies pairs of load or store instructions
11-
// operating on consecutive memory locations and merges them into a single
12-
// paired instruction, taking advantage of hardware support for paired
13-
// accesses. Much of the pairing logic is adapted from the
14-
// AArch64LoadStoreOpt pass.
15-
// 2. Load/Store Bonding: When direct pairing cannot be applied, the pass
16-
// bonds related memory instructions together into a bundle. This preserves
17-
// their proximity and prevents reordering that might violate memory
18-
// semantics. This technique benefits certain targets (e.g. MIPS P8700) by
19-
// ensuring that paired or bonded memory operations remain contiguous.
9+
// Load/Store Pairing: It identifies pairs of load or store instructions
10+
// operating on consecutive memory locations and merges them into a single
11+
// paired instruction, leveraging hardware support for paired memory accesses.
12+
// Much of the pairing logic is adapted from the AArch64LoadStoreOpt pass.
2013
//
2114
// NOTE: The AArch64LoadStoreOpt pass performs additional optimizations such as
22-
// merging zero store instructions, promoting loads that read directly
23-
// from a preceding store, and merging base register updates with
24-
// load/store instructions (via pre-/post-indexed addressing). These
25-
// advanced transformations are not yet implemented in the RISC-V pass but
26-
// represent potential future enhancements, as similar benefits could be
27-
// achieved on RISC-V architectures.
15+
// merging zero store instructions, promoting loads that read directly from a
16+
// preceding store, and merging base register updates with load/store
17+
// instructions (via pre-/post-indexed addressing). These advanced
18+
// transformations are not yet implemented in the RISC-V pass but represent
19+
// potential future enhancements for further optimizing RISC-V memory
20+
// operations.
2821
//
2922
//===----------------------------------------------------------------------===//
3023

@@ -90,7 +83,6 @@ struct RISCVLoadStoreOpt : public MachineFunctionPass {
9083
const RISCVRegisterInfo *TRI;
9184
LiveRegUnits ModifiedRegUnits, UsedRegUnits;
9285
bool EnableLoadStorePairs = false;
93-
bool EnableLoadStoreBonding = false;
9486
};
9587
} // end anonymous namespace
9688

@@ -103,8 +95,7 @@ bool RISCVLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
10395
return false;
10496
const RISCVSubtarget &Subtarget = Fn.getSubtarget<RISCVSubtarget>();
10597
EnableLoadStorePairs = Subtarget.useLoadStorePairs();
106-
EnableLoadStoreBonding = Subtarget.useMIPSLoadStoreBonding();
107-
if (!EnableLoadStorePairs && !EnableLoadStoreBonding)
98+
if (!EnableLoadStorePairs)
10899
return false;
109100

110101
bool MadeChange = false;
@@ -379,19 +370,9 @@ RISCVLoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
379370
First = InsertionPoint;
380371
}
381372

382-
// It may pair them or creaate bundles. The instructions may still be bundled
383-
// together, preserving their proximity and the intent of keeping related
384-
// memory accesses together. This bundling can help subsequent passes maintain
385-
// any implicit ordering or avoid reordering that might violate memory
386-
// semantics. For exmaple, MIPS P8700 benefits from it.
387373
if (EnableLoadStorePairs && tryConvertToLdStPair(First, Second)) {
388374
LLVM_DEBUG(dbgs() << "Pairing load/store:\n ");
389375
LLVM_DEBUG(prev_nodbg(NextI, MBB.begin())->print(dbgs()));
390-
} else if (EnableLoadStoreBonding) {
391-
finalizeBundle(MBB, First.getInstrIterator(),
392-
std::next(Second).getInstrIterator());
393-
LLVM_DEBUG(dbgs() << "Bonding load/store:\n ");
394-
LLVM_DEBUG(prev_nodbg(NextI, MBB.begin())->print(dbgs()));
395376
}
396377

397378
return NextI;

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp‎

Lines changed: 5 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -63,18 +63,13 @@ static cl::opt<unsigned> RISCVMinimumJumpTableEntries(
6363
cl::desc("Set minimum number of entries to use a jump table on RISCV"));
6464

6565
static cl::opt<bool> UseMIPSLoadStorePairsOpt(
66-
"mips-riscv-load-store-pairs",
67-
cl::desc("RISCV: Enable the load/store pair optimization pass"),
68-
cl::init(false), cl::Hidden);
69-
70-
static cl::opt<bool> UseMIPSLoadStoreBondingOpt(
71-
"mips-riscv-load-store-bonding",
72-
cl::desc("RISCV: Optimize for load-store bonding"), cl::init(true),
66+
"riscv-mips-load-store-pairs",
67+
cl::desc("Enable the load/store pair optimization pass"), cl::init(false),
7368
cl::Hidden);
7469

75-
static cl::opt<bool>
76-
UseCCMovInsn("riscv-ccmov", cl::desc("RISCV: Use 'mips.ccmov' instruction"),
77-
cl::init(true), cl::Hidden);
70+
static cl::opt<bool> UseCCMovInsn("riscv-ccmov",
71+
cl::desc("Use 'mips.ccmov' instruction"),
72+
cl::init(true), cl::Hidden);
7873

7974
void RISCVSubtarget::anchor() {}
8075

@@ -257,10 +252,6 @@ bool RISCVSubtarget::useLoadStorePairs() const {
257252
return UseMIPSLoadStorePairsOpt && HasVendorXMIPSLSP;
258253
}
259254

260-
bool RISCVSubtarget::useMIPSLoadStoreBonding() const {
261-
return UseMIPSLoadStoreBondingOpt && HasVendorXMIPSLSP;
262-
}
263-
264255
bool RISCVSubtarget::useCCMovInsn() const {
265256
return UseCCMovInsn && HasVendorXMIPSCMove;
266257
}

‎llvm/lib/Target/RISCV/RISCVSubtarget.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -189,7 +189,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
189189
return is64Bit() ? 64 : 32;
190190
}
191191
bool useLoadStorePairs() const;
192-
bool useMIPSLoadStoreBonding() const;
193192
bool useCCMovInsn() const;
194193
unsigned getFLen() const {
195194
if (HasStdExtD)

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -313,8 +313,7 @@ RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
313313
ScheduleDAGMI *DAG = nullptr;
314314
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
315315
bool EnableLoadStoreClusteringForLoadStoreOpt =
316-
!ST.getMacroFusions().empty() &&
317-
(ST.useLoadStorePairs() || ST.useMIPSLoadStoreBonding());
316+
!ST.getMacroFusions().empty() && ST.useLoadStorePairs();
318317

319318
if (EnablePostMISchedLoadStoreClustering ||
320319
EnableLoadStoreClusteringForLoadStoreOpt) {
@@ -572,11 +571,6 @@ void RISCVPassConfig::addPreEmitPass() {
572571
addPass(createMachineCopyPropagationPass(true));
573572
addPass(&BranchRelaxationPassID);
574573
addPass(createRISCVMakeCompressibleOptPass());
575-
576-
// LoadStoreOptimizer creates bundles for load-store bonding.
577-
addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
578-
return MF.getSubtarget<RISCVSubtarget>().useMIPSLoadStoreBonding();
579-
}));
580574
}
581575

582576
void RISCVPassConfig::addPreEmitPass2() {

‎llvm/test/CodeGen/RISCV/O0-pipeline.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,6 @@
6464
; CHECK-NEXT: Implement the 'patchable-function' attribute
6565
; CHECK-NEXT: Branch relaxation pass
6666
; CHECK-NEXT: RISC-V Make Compressible
67-
; CHECK-NEXT: Unpack machine instruction bundles
6867
; CHECK-NEXT: Contiguously Lay Out Funclets
6968
; CHECK-NEXT: Remove Loads Into Fake Uses
7069
; CHECK-NEXT: StackMap Liveness Analysis

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,6 @@
195195
; CHECK-NEXT: Machine Copy Propagation Pass
196196
; CHECK-NEXT: Branch relaxation pass
197197
; CHECK-NEXT: RISC-V Make Compressible
198-
; CHECK-NEXT: Unpack machine instruction bundles
199198
; CHECK-NEXT: Contiguously Lay Out Funclets
200199
; CHECK-NEXT: Remove Loads Into Fake Uses
201200
; CHECK-NEXT: StackMap Liveness Analysis

‎llvm/test/CodeGen/RISCV/load-store-pair.ll‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,15 @@
88
; RUN: | FileCheck %s -check-prefix=RV64I
99
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+d -verify-machineinstrs < %s \
1010
; RUN: | FileCheck %s -check-prefix=RV64D
11-
; RUN: llc -mtriple=riscv32 -mattr=+Xmipslsp -mips-riscv-load-store-pairs=1 -verify-machineinstrs < %s \
11+
; RUN: llc -mtriple=riscv32 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1212
; RUN: | FileCheck %s -check-prefix=RV32I_PAIR
13-
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+d,+Xmipslsp -mips-riscv-load-store-pairs=1 -verify-machineinstrs < %s \
13+
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+d,+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1414
; RUN: | FileCheck %s -check-prefix=RV32D_PAIR
15-
; RUN: llc -mtriple=riscv64 -mattr=+Xmipslsp -mips-riscv-load-store-pairs=1 -verify-machineinstrs < %s \
15+
; RUN: llc -mtriple=riscv64 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1616
; RUN: | FileCheck %s -check-prefix=RV64I_PAIR
17-
; RUN: llc -mtriple=riscv64 -mcpu mips-p8700 -mattr=+Xmipslsp -mips-riscv-load-store-pairs=1 -verify-machineinstrs < %s \
17+
; RUN: llc -mtriple=riscv64 -mcpu mips-p8700 -mattr=+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
1818
; RUN: | FileCheck %s -check-prefix=RV64P_8700
19-
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+d,+Xmipslsp -mips-riscv-load-store-pairs=1 -verify-machineinstrs < %s \
19+
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+d,+Xmipslsp -riscv-mips-load-store-pairs=1 -verify-machineinstrs < %s \
2020
; RUN: | FileCheck %s -check-prefix=RV64D_PAIR
2121
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+d -verify-machineinstrs < %s \
2222
; RUN: | FileCheck %s -check-prefix=RV64D_8700

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