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ppenzinwangpc-pp
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Co-authored-by: Pengcheng Wang <[email protected]>
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llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td

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Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ def TTAscalonD8Model : SchedMachineModel {
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let CompleteModel = 0;
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// TODO supported, but haven't added scheduling info yet
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// TODO: supported, but haven't added scheduling info yet.
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
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HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
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HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
@@ -35,7 +35,7 @@ let BufferSize = 16 in {
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def AscalonFXC : ProcResource<2>; // ALU, BR
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def AscalonFXD : ProcResource<2>; // ALU
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def AscalonFP : ProcResource<2>;
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// TODO two vector units with vector scheduling model
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// TODO: two vector units with vector scheduling model.
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}
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def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXD]>;

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