Revert "XXX - Use computeKnownBits for the general case"

This reverts commit e3d348374fa67b6daa09d5838d09eed8fe0dc083.

Author: arsenm

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -13988,11 +13988,16 @@ SDValue SITargetLowering::tryFoldToMad64_32(SDNode *N,
 SDValue
 SITargetLowering::foldAddSub64WithZeroLowBitsTo32(SDNode *N,
                                                   DAGCombinerInfo &DCI) const {
-  SelectionDAG &DAG = DCI.DAG;
   SDValue RHS = N->getOperand(1);
-  KnownBits KB = DAG.computeKnownBits(RHS);
+  auto *CRHS = dyn_cast<ConstantSDNode>(RHS);
+  if (!CRHS)
+    return SDValue();
 
-  if (KB.countMinTrailingZeros() >= 32) {
+  // TODO: Worth using computeKnownBits? Maybe expensive since it's so
+  // common.
+  uint64_t Val = CRHS->getZExtValue();
+  if (countr_zero(Val) >= 32) {
+    SelectionDAG &DAG = DCI.DAG;
     SDLoc SL(N);
     SDValue LHS = N->getOperand(0);
 
@@ -14006,7 +14011,7 @@ SITargetLowering::foldAddSub64WithZeroLowBitsTo32(SDNode *N,
     // to interfere with addressing mode patterns.
 
     SDValue Hi = getHiHalf64(LHS, DAG);
-    SDValue ConstHi32 = getHiHalf64(RHS, DAG);
+    SDValue ConstHi32 = DAG.getConstant(Hi_32(Val), SL, MVT::i32);
     SDValue AddHi =
         DAG.getNode(N->getOpcode(), SL, MVT::i32, Hi, ConstHi32, N->getFlags());
 

llvm/test/CodeGen/AMDGPU/add64-low-32-bits-known-zero.ll

@@ -170,7 +170,8 @@ define i64 @v_add_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) {
 ; GFX9-LABEL: v_add_i64_variable_high_bits_known0_0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0, v0
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %zext.offset.hi32 = zext i32 %offset.hi32 to i64
   %in.high.bits = shl i64 %zext.offset.hi32, 32
@@ -182,7 +183,8 @@ define i64 @v_add_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) {
 define amdgpu_ps i64 @s_add_i64_variable_high_bits_known0_0(i64 inreg %reg, i32 inreg %offset.hi32) {
 ; GFX9-LABEL: s_add_i64_variable_high_bits_known0_0:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_add_i32 s1, s1, s2
+; GFX9-NEXT:    s_add_u32 s0, s0, 0
+; GFX9-NEXT:    s_addc_u32 s1, s1, s2
 ; GFX9-NEXT:    ; return to shader part epilog
   %zext.offset.hi32 = zext i32 %offset.hi32 to i64
   %in.high.bits = shl i64 %zext.offset.hi32, 32

llvm/test/CodeGen/AMDGPU/sub64-low-32-bits-known-zero.ll

@@ -170,7 +170,8 @@ define i64 @v_sub_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) {
 ; GFX9-LABEL: v_sub_i64_variable_high_bits_known0_0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    v_sub_u32_e32 v1, v1, v2
+; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, 0, v0
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %zext.offset.hi32 = zext i32 %offset.hi32 to i64
   %in.high.bits = shl i64 %zext.offset.hi32, 32
@@ -182,7 +183,8 @@ define i64 @v_sub_i64_variable_high_bits_known0_0(i64 %reg, i32 %offset.hi32) {
 define amdgpu_ps i64 @s_sub_i64_variable_high_bits_known0_0(i64 inreg %reg, i32 inreg %offset.hi32) {
 ; GFX9-LABEL: s_sub_i64_variable_high_bits_known0_0:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_sub_i32 s1, s1, s2
+; GFX9-NEXT:    s_sub_u32 s0, s0, 0
+; GFX9-NEXT:    s_subb_u32 s1, s1, s2
 ; GFX9-NEXT:    ; return to shader part epilog
   %zext.offset.hi32 = zext i32 %offset.hi32 to i64
   %in.high.bits = shl i64 %zext.offset.hi32, 32