Delete NVPTXISelLowering implementation

Author: justinfargnoli

llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

@@ -725,7 +725,7 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
   // We have some custom DAG combine patterns for these nodes
   setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD,
                        ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM,
-                       ISD::TRUNCATE, ISD::VSELECT});
+                       ISD::VSELECT});
 
   // setcc for f16x2 and bf16x2 needs special handling to prevent
   // legalizer's attempt to scalarize it due to v2i1 not being legal.
@@ -5601,53 +5601,6 @@ static SDValue PerformREMCombine(SDNode *N,
   return SDValue();
 }
 
-// truncate (logic_op x, y) --> logic_op (truncate x), (truncate y)
-// This will reduce register pressure.
-static SDValue PerformTruncCombine(SDNode *N,
-                                   TargetLowering::DAGCombinerInfo &DCI) {
-  if (!DCI.isBeforeLegalizeOps())
-    return SDValue();
-
-  SDValue LogicalOp = N->getOperand(0);
-  switch (LogicalOp.getOpcode()) {
-  default:
-    break;
-  case ISD::ADD:
-  case ISD::SUB:
-  case ISD::MUL:
-  case ISD::AND:
-  case ISD::OR:
-  case ISD::XOR: {
-    EVT VT = N->getValueType(0);
-    EVT LogicalVT = LogicalOp.getValueType();
-    if (VT != MVT::i32 || LogicalVT != MVT::i64)
-      break;
-    const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
-    if (!VT.isScalarInteger() &&
-        !TLI.isOperationLegal(LogicalOp.getOpcode(), VT))
-      break;
-    if (!all_of(LogicalOp.getNode()->uses(), [](SDNode *U) {
-          return U->isMachineOpcode()
-                     ? U->getMachineOpcode() == NVPTX::CVT_u32_u64
-                     : U->getOpcode() == ISD::TRUNCATE;
-        }))
-      break;
-
-    SDLoc DL(N);
-    SDValue CVTNone =
-        DCI.DAG.getTargetConstant(NVPTX::PTXCvtMode::NONE, DL, MVT::i32);
-    SDNode *NarrowL = DCI.DAG.getMachineNode(NVPTX::CVT_u32_u64, DL, VT,
-                                             LogicalOp.getOperand(0), CVTNone);
-    SDNode *NarrowR = DCI.DAG.getMachineNode(NVPTX::CVT_u32_u64, DL, VT,
-                                             LogicalOp.getOperand(1), CVTNone);
-    return DCI.DAG.getNode(LogicalOp.getOpcode(), DL, VT, SDValue(NarrowL, 0),
-                           SDValue(NarrowR, 0));
-  }
-  }
-
-  return SDValue();
-}
-
 enum OperandSignedness {
   Signed = 0,
   Unsigned,
@@ -6064,8 +6017,6 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
     case ISD::UREM:
     case ISD::SREM:
       return PerformREMCombine(N, DCI, OptLevel);
-    case ISD::TRUNCATE:
-      return PerformTruncCombine(N, DCI);
     case ISD::SETCC:
       return PerformSETCCCombine(N, DCI, STI.getSmVersion());
     case ISD::LOAD:
@@ -6084,9 +6035,6 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
       return PerformVSELECTCombine(N, DCI);
   }
 
-  if (N->isMachineOpcode() && N->getMachineOpcode() == NVPTX::CVT_u32_u64)
-    return PerformTruncCombine(N, DCI);
-
   return SDValue();
 }