Use getMaxNumVectorRegs instead of getArchVGPRAllocationThreshold

Change-Id: I36e92840e35774cb419389ee6dadc26dd376ebaa

Author: jrbyrnes

llvm/lib/Target/AMDGPU/GCNRegPressure.cpp

@@ -99,7 +99,8 @@ void GCNRegPressure::inc(unsigned Reg,
 bool GCNRegPressure::less(const MachineFunction &MF, const GCNRegPressure &O,
                           unsigned MaxOccupancy) const {
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
-  unsigned ArchVGPRThreshold = ST.getArchVGPRAllocationThreshold(MF);
+  unsigned ArchVGPRThreshold =
+      ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first;
   unsigned DynamicVGPRBlockSize =
       MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
 
@@ -250,7 +251,8 @@ bool GCNRegPressure::less(const MachineFunction &MF, const GCNRegPressure &O,
 Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST,
                       unsigned DynamicVGPRBlockSize,
                       const MachineFunction *MF) {
-  unsigned ArchVGPRThreshold = ST->getArchVGPRAllocationThreshold(*MF);
+  unsigned ArchVGPRThreshold =
+      ST->getRegisterInfo()->getMaxNumVectorRegs(*MF).first;
   return Printable(
       [&RP, ST, DynamicVGPRBlockSize, ArchVGPRThreshold, MF](raw_ostream &OS) {
         OS << "VGPRs: " << RP.getArchVGPRNum(ArchVGPRThreshold) << ' '
@@ -903,10 +905,10 @@ bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
   auto printRP = [&MF](const GCNRegPressure &RP) {
     return Printable([&RP, &MF](raw_ostream &OS) {
       OS << format(PFX "  %-5d", RP.getSGPRNum())
-         << format(
-                " %-5d",
-                RP.getVGPRNum(false, MF.getSubtarget<GCNSubtarget>()
-                                         .getArchVGPRAllocationThreshold(MF)));
+         << format(" %-5d", RP.getVGPRNum(false, MF.getSubtarget<GCNSubtarget>()
+                                                     .getRegisterInfo()
+                                                     ->getMaxNumVectorRegs(MF)
+                                                     .first));
     });
   };
 

llvm/lib/Target/AMDGPU/GCNRegPressure.h

@@ -89,7 +89,6 @@ struct GCNRegPressure {
         getAVGPRsAsVGPRsNum(NumArchVGPRs, NumAVGPRs, AddressableArchVGPR);
     unsigned AVGPRsAsAGPRs = getAVGPRsAsAGPRsNum(
         NumArchVGPRs, NumAGPRs, NumAVGPRs, AddressableArchVGPR);
-    NumAVGPRs > AVGPRsAsVGPRs ? NumAVGPRs - AVGPRsAsVGPRs : 0;
     return alignTo(NumArchVGPRs + AVGPRsAsVGPRs,
                    AMDGPU::IsaInfo::getArchVGPRAllocGranule()) +
            NumAGPRs + AVGPRsAsAGPRs;
@@ -129,11 +128,12 @@ struct GCNRegPressure {
     unsigned DynamicVGPRBlockSize =
         MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
 
-    return std::min(ST.getOccupancyWithNumSGPRs(getSGPRNum()),
-                    ST.getOccupancyWithNumVGPRs(
-                        getVGPRNum(ST.hasGFX90AInsts(),
-                                   ST.getArchVGPRAllocationThreshold(MF)),
-                        DynamicVGPRBlockSize));
+    return std::min(
+        ST.getOccupancyWithNumSGPRs(getSGPRNum()),
+        ST.getOccupancyWithNumVGPRs(
+            getVGPRNum(ST.hasGFX90AInsts(),
+                       ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first),
+            DynamicVGPRBlockSize));
   }
 
   void inc(unsigned Reg,

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -190,9 +190,10 @@ static void getRegisterPressures(
     TempUpwardTracker.recede(*MI);
     NewPressure = TempUpwardTracker.getPressure();
   }
-  unsigned ArchVGPRThreshold =
-      DAG->MF.getSubtarget<GCNSubtarget>().getArchVGPRAllocationThreshold(
-          DAG->MF);
+  unsigned ArchVGPRThreshold = DAG->MF.getSubtarget<GCNSubtarget>()
+                                   .getRegisterInfo()
+                                   ->getMaxNumVectorRegs(DAG->MF)
+                                   .first;
   Pressure[AMDGPU::RegisterPressureSets::SReg_32] = NewPressure.getSGPRNum();
   Pressure[AMDGPU::RegisterPressureSets::VGPR_32] =
       NewPressure.getArchVGPRNum(ArchVGPRThreshold);
@@ -343,9 +344,11 @@ void GCNSchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
                             ? static_cast<GCNRPTracker *>(&UpwardTracker)
                             : static_cast<GCNRPTracker *>(&DownwardTracker);
       SGPRPressure = T->getPressure().getSGPRNum();
-      VGPRPressure = T->getPressure().getArchVGPRNum(
-          DAG->MF.getSubtarget<GCNSubtarget>().getArchVGPRAllocationThreshold(
-              DAG->MF));
+      VGPRPressure =
+          T->getPressure().getArchVGPRNum(DAG->MF.getSubtarget<GCNSubtarget>()
+                                              .getRegisterInfo()
+                                              ->getMaxNumVectorRegs(DAG->MF)
+                                              .first);
     }
   }
   ReadyQueue &Q = Zone.Available;
@@ -1286,7 +1289,8 @@ void GCNSchedStage::checkScheduling() {
                     << print(PressureAfter, &ST, 0, &MF));
   LLVM_DEBUG(dbgs() << "Region: " << RegionIdx << ".\n");
 
-  unsigned ArchVGPRThreshold = ST.getArchVGPRAllocationThreshold(MF);
+  unsigned ArchVGPRThreshold =
+      ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first;
   if (PressureAfter.getSGPRNum() <= S.SGPRCriticalLimit &&
       PressureAfter.getVGPRNum(ST.hasGFX90AInsts(), ArchVGPRThreshold) <=
           S.VGPRCriticalLimit) {
@@ -1478,7 +1482,8 @@ bool GCNSchedStage::shouldRevertScheduling(unsigned WavesAfter) {
 
   // For dynamic VGPR mode, we don't want to waste any VGPR blocks.
   if (DAG.MFI.isDynamicVGPREnabled()) {
-    unsigned ArchVGPRThreshold = ST.getArchVGPRAllocationThreshold(MF);
+    unsigned ArchVGPRThreshold =
+        ST.getRegisterInfo()->getMaxNumVectorRegs(MF).first;
     unsigned BlocksBefore = AMDGPU::IsaInfo::getAllocatedNumVGPRBlocks(
         &ST, DAG.MFI.getDynamicVGPRBlockSize(),
         PressureBefore.getVGPRNum(false, ArchVGPRThreshold));

llvm/lib/Target/AMDGPU/GCNSubtarget.h

@@ -1629,15 +1629,6 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
     return AMDGPU::IsaInfo::getAddressableNumArchVGPRs(this);
   }
 
-  unsigned getArchVGPRAllocationThreshold(const MachineFunction &MF) const {
-    if (hasGFX90AInsts() || !hasMAIInsts())
-      return AMDGPU::IsaInfo::getAddressableNumArchVGPRs(this);
-
-    const Function &F = MF.getFunction();
-    std::pair<unsigned, unsigned> Waves = getWavesPerEU(F);
-    return getMaxNumVGPRs(Waves.first, 0);
-  }
-
   /// \returns Addressable number of VGPRs supported by the subtarget.
   unsigned getAddressableNumVGPRs(unsigned DynamicVGPRBlockSize) const {
     return AMDGPU::IsaInfo::getAddressableNumVGPRs(this, DynamicVGPRBlockSize);

llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp

@@ -209,8 +209,9 @@ bool SIFormMemoryClausesImpl::checkPressure(const MachineInstr &MI,
   // tracking does not account for the alignment requirements for SGPRs, or the
   // fragmentation of registers the allocator will need to satisfy.
   if (Occupancy >= MFI->getMinAllowedOccupancy() &&
-      MaxPressure.getVGPRNum(ST->hasGFX90AInsts(),
-                             ST->getArchVGPRAllocationThreshold(*MI.getMF())) <=
+      MaxPressure.getVGPRNum(
+          ST->hasGFX90AInsts(),
+          ST->getRegisterInfo()->getMaxNumVectorRegs(*MI.getMF()).first) <=
           MaxVGPRs / 2 &&
       MaxPressure.getSGPRNum() <= MaxSGPRs / 2) {
     LastRecordedOccupancy = Occupancy;