Work to fix regressions in integer select srcmod generation when v2i32

is made legal for or/xor/and.

Complete fix of v2i32 in VOP SrcMod placement.

Author: chrisjbris

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

@@ -3059,36 +3059,62 @@ bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
     Src = Src.getOperand(0);
   }
 
+  // v2i32 xor/or/and are legal. A vselect using these instructions as operands
+  // is scalarised into two selects with EXTRACT_VECTOR_ELT operands. Peek
+  // through this extract if possible.
+  auto getVectorBitWiseOp = [](SDValue S) -> SDValue {
+    if (S->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
+      SDValue VecOp = S->getOperand(0);
+      if (VecOp.getOpcode() == ISD::XOR || VecOp.getOpcode() == ISD::AND ||
+          VecOp.getOpcode() == ISD::OR)
+        return VecOp;
+    }
+    return SDValue();
+  };
+
+  SDValue Vec = getVectorBitWiseOp(Src);
+  SDValue BWSrc = Vec ? Vec : Src;
   // Convert various sign-bit masks to src mods. Currently disabled for 16-bit
   // types as the codegen replaces the operand without adding a srcmod.
   // This is intentionally finding the cases where we are performing float neg
   // and abs on int types, the goal is not to obtain two's complement neg or
   // abs.
   // TODO: Add 16-bit support.
-  unsigned Opc = Src->getOpcode();
+  unsigned Opc = Vec ? Vec->getOpcode() : Src->getOpcode();
   EVT VT = Src.getValueType();
   if ((Opc != ISD::AND && Opc != ISD::OR && Opc != ISD::XOR) ||
       (VT != MVT::i32 && VT != MVT::v2i32 && VT != MVT::i64))
     return true;
 
-  ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Src->getOperand(1));
+  ConstantSDNode *CRHS =
+      isConstOrConstSplat(Vec ? Vec->getOperand(1) : Src->getOperand(1));
   if (!CRHS)
     return true;
 
+  auto ReplaceSrc = [&]() -> SDValue {
+    if (Vec) {
+      SDValue LHS = BWSrc->getOperand(0);
+      SDValue Index = Src->getOperand(1);
+      return Src = CurDAG->getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Src),
+                                   Src.getValueType(), LHS, Index);
+    }
+    return Src = BWSrc.getOperand(0);
+  };
+
   // Recognise (xor a, 0x80000000) as NEG SrcMod.
   // Recognise (and a, 0x7fffffff) as ABS SrcMod.
   // Recognise (or a, 0x80000000) as NEG+ABS SrcModifiers.
   if (Opc == ISD::XOR && CRHS->getAPIntValue().isSignMask()) {
     Mods |= SISrcMods::NEG;
-    Src = Src.getOperand(0);
+    Src = ReplaceSrc();
   } else if (Opc == ISD::AND && AllowAbs &&
              CRHS->getAPIntValue().isMaxSignedValue()) {
     Mods |= SISrcMods::ABS;
-    Src = Src.getOperand(0);
+    Src = ReplaceSrc();
   } else if (Opc == ISD::OR && AllowAbs && CRHS->getAPIntValue().isSignMask()) {
     Mods |= SISrcMods::ABS;
     Mods |= SISrcMods::NEG;
-    Src = Src.getOperand(0);
+    Src = ReplaceSrc();
   }
 
   return true;

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

@@ -4251,12 +4251,12 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
              (ElementType.getSizeInBits() - 1)) {
     ShiftAmt = ShiftFullAmt;
   } else {
-    SDValue truncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, TargetType, RHS);
+    SDValue TruncShiftAmt = DAG.getNode(ISD::TRUNCATE, SL, TargetType, RHS);
     const SDValue ShiftMask =
         DAG.getConstant(TargetScalarType.getSizeInBits() - 1, SL, TargetType);
     // This AND instruction will clamp out of bounds shift values.
     // It will also be removed during later instruction selection.
-    ShiftAmt = DAG.getNode(ISD::AND, SL, TargetType, truncShiftAmt, ShiftMask);
+    ShiftAmt = DAG.getNode(ISD::AND, SL, TargetType, TruncShiftAmt, ShiftMask);
   }
 
   EVT ConcatType;
@@ -4313,16 +4313,8 @@ SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
   return DAG.getNode(ISD::BITCAST, SL, VT, Vec);
 }
 
-SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
-                                                DAGCombinerInfo &DCI) const {
-  SDValue RHS = N->getOperand(1);
-  ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
-  EVT VT = N->getValueType(0);
-  SDValue LHS = N->getOperand(0);
-  SelectionDAG &DAG = DCI.DAG;
-  SDLoc SL(N);
-  unsigned RHSVal;
-
+static SDValue getScalarisedShift(SDValue LHS, SDValue RHS, SelectionDAG &DAG) {
+  SDLoc SL = SDLoc(RHS);
   if (RHS->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
     SDValue VAND = RHS.getOperand(0);
     if (ConstantSDNode *CRRHS = dyn_cast<ConstantSDNode>(RHS->getOperand(1))) {
@@ -4359,12 +4351,26 @@ SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
             SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
             if (AndIndex == 0 || AndIndex == 1)
               return DAG.getNode(ISD::SRL, SL, MVT::i32, Trunc,
-                                 AndIndex == 0 ? LoAnd : HiAnd, N->getFlags());
+                                 AndIndex == 0 ? LoAnd : HiAnd, RHS->getFlags());
           }
         }
       }
     }
   }
+  return SDValue();
+}
+
+SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
+                                                DAGCombinerInfo &DCI) const {
+  SDValue RHS = N->getOperand(1);
+  ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
+  EVT VT = N->getValueType(0);
+  SDValue LHS = N->getOperand(0);
+  SelectionDAG &DAG = DCI.DAG;
+  SDLoc SL(N);
+  unsigned RHSVal;
+
+
 
   if (CRHS) {
     RHSVal = CRHS->getZExtValue();