Skip to content

Commit 5799dbd

Browse files
easyonaaditeasyonaadit
committed
removing unused variable
1 parent abee4b5 commit 5799dbd

File tree

5 files changed

+0
-854
lines changed

5 files changed

+0
-854
lines changed

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5276,7 +5276,6 @@ static MachineBasicBlock *Expand64BitScalarArithmetic(MachineInstr &MI,
52765276
// For GFX12, we emit s_add_u64 and s_sub_u64.
52775277
MachineFunction *MF = BB->getParent();
52785278
const SIInstrInfo *TII = MF->getSubtarget<GCNSubtarget>().getInstrInfo();
5279-
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
52805279
const GCNSubtarget &ST = MF->getSubtarget<GCNSubtarget>();
52815280
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
52825281
const DebugLoc &DL = MI.getDebugLoc();
@@ -5408,15 +5407,6 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
54085407
RetBB = &BB;
54095408
break;
54105409
}
5411-
case AMDGPU::V_CMP_LT_U64_e64: // umin
5412-
case AMDGPU::V_CMP_LT_I64_e64: // min
5413-
case AMDGPU::V_CMP_GT_U64_e64: // umax
5414-
case AMDGPU::V_CMP_GT_I64_e64: { // max
5415-
// Idempotent operations.
5416-
BuildMI(BB, MI, DL, TII->get(AMDGPU::S_MOV_B64), DstReg).addReg(SrcReg);
5417-
RetBB = &BB;
5418-
break;
5419-
}
54205410
case AMDGPU::S_XOR_B32:
54215411
case AMDGPU::S_ADD_I32:
54225412
case AMDGPU::S_ADD_U64_PSEUDO:

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll‎

Lines changed: 0 additions & 188 deletions
Original file line numberDiff line numberDiff line change
@@ -1269,21 +1269,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
12691269
; GFX8DAGISEL-LABEL: divergent_value_i64:
12701270
; GFX8DAGISEL: ; %bb.0: ; %entry
12711271
; GFX8DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1272-
<<<<<<< HEAD
1273-
<<<<<<< HEAD
12741272
; GFX8DAGISEL-NEXT: s_mov_b32 s4, 0
12751273
; GFX8DAGISEL-NEXT: s_brev_b32 s5, 1
12761274
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1277-
=======
1278-
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1279-
; GFX8DAGISEL-NEXT: s_brev_b32 s5, 1
1280-
; GFX8DAGISEL-NEXT: s_mov_b32 s4, 0
1281-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1282-
=======
1283-
; GFX8DAGISEL-NEXT: s_mov_b32 s4, 0
1284-
; GFX8DAGISEL-NEXT: s_brev_b32 s5, 1
1285-
; GFX8DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1286-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
12871275
; GFX8DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
12881276
; GFX8DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
12891277
; GFX8DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1306,21 +1294,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
13061294
; GFX8GISEL-LABEL: divergent_value_i64:
13071295
; GFX8GISEL: ; %bb.0: ; %entry
13081296
; GFX8GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1309-
<<<<<<< HEAD
1310-
<<<<<<< HEAD
1311-
; GFX8GISEL-NEXT: s_mov_b32 s4, 0
1312-
; GFX8GISEL-NEXT: s_brev_b32 s5, 1
1313-
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
1314-
=======
1315-
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
1316-
; GFX8GISEL-NEXT: s_brev_b32 s5, 1
1317-
; GFX8GISEL-NEXT: s_mov_b32 s4, 0
1318-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1319-
=======
13201297
; GFX8GISEL-NEXT: s_mov_b32 s4, 0
13211298
; GFX8GISEL-NEXT: s_brev_b32 s5, 1
13221299
; GFX8GISEL-NEXT: s_mov_b64 s[6:7], exec
1323-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
13241300
; GFX8GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
13251301
; GFX8GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
13261302
; GFX8GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1343,21 +1319,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
13431319
; GFX9DAGISEL-LABEL: divergent_value_i64:
13441320
; GFX9DAGISEL: ; %bb.0: ; %entry
13451321
; GFX9DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1346-
<<<<<<< HEAD
1347-
<<<<<<< HEAD
1348-
; GFX9DAGISEL-NEXT: s_mov_b32 s4, 0
1349-
; GFX9DAGISEL-NEXT: s_brev_b32 s5, 1
1350-
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1351-
=======
1352-
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1353-
; GFX9DAGISEL-NEXT: s_brev_b32 s5, 1
1354-
; GFX9DAGISEL-NEXT: s_mov_b32 s4, 0
1355-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1356-
=======
13571322
; GFX9DAGISEL-NEXT: s_mov_b32 s4, 0
13581323
; GFX9DAGISEL-NEXT: s_brev_b32 s5, 1
13591324
; GFX9DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1360-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
13611325
; GFX9DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
13621326
; GFX9DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
13631327
; GFX9DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1380,21 +1344,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
13801344
; GFX9GISEL-LABEL: divergent_value_i64:
13811345
; GFX9GISEL: ; %bb.0: ; %entry
13821346
; GFX9GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1383-
<<<<<<< HEAD
1384-
<<<<<<< HEAD
1385-
; GFX9GISEL-NEXT: s_mov_b32 s4, 0
1386-
; GFX9GISEL-NEXT: s_brev_b32 s5, 1
1387-
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
1388-
=======
1389-
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
1390-
; GFX9GISEL-NEXT: s_brev_b32 s5, 1
1391-
; GFX9GISEL-NEXT: s_mov_b32 s4, 0
1392-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1393-
=======
13941347
; GFX9GISEL-NEXT: s_mov_b32 s4, 0
13951348
; GFX9GISEL-NEXT: s_brev_b32 s5, 1
13961349
; GFX9GISEL-NEXT: s_mov_b64 s[6:7], exec
1397-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
13981350
; GFX9GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
13991351
; GFX9GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
14001352
; GFX9GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1417,21 +1369,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
14171369
; GFX1064DAGISEL-LABEL: divergent_value_i64:
14181370
; GFX1064DAGISEL: ; %bb.0: ; %entry
14191371
; GFX1064DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1420-
<<<<<<< HEAD
1421-
<<<<<<< HEAD
1422-
; GFX1064DAGISEL-NEXT: s_mov_b32 s4, 0
1423-
; GFX1064DAGISEL-NEXT: s_brev_b32 s5, 1
1424-
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1425-
=======
1426-
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1427-
; GFX1064DAGISEL-NEXT: s_brev_b32 s5, 1
1428-
; GFX1064DAGISEL-NEXT: s_mov_b32 s4, 0
1429-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1430-
=======
14311372
; GFX1064DAGISEL-NEXT: s_mov_b32 s4, 0
14321373
; GFX1064DAGISEL-NEXT: s_brev_b32 s5, 1
14331374
; GFX1064DAGISEL-NEXT: s_mov_b64 s[6:7], exec
1434-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
14351375
; GFX1064DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
14361376
; GFX1064DAGISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
14371377
; GFX1064DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1453,21 +1393,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
14531393
; GFX1064GISEL-LABEL: divergent_value_i64:
14541394
; GFX1064GISEL: ; %bb.0: ; %entry
14551395
; GFX1064GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1456-
<<<<<<< HEAD
1457-
<<<<<<< HEAD
14581396
; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
14591397
; GFX1064GISEL-NEXT: s_brev_b32 s5, 1
14601398
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
1461-
=======
1462-
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
1463-
; GFX1064GISEL-NEXT: s_brev_b32 s5, 1
1464-
; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
1465-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1466-
=======
1467-
; GFX1064GISEL-NEXT: s_mov_b32 s4, 0
1468-
; GFX1064GISEL-NEXT: s_brev_b32 s5, 1
1469-
; GFX1064GISEL-NEXT: s_mov_b64 s[6:7], exec
1470-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
14711399
; GFX1064GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
14721400
; GFX1064GISEL-NEXT: s_ff1_i32_b64 s12, s[6:7]
14731401
; GFX1064GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1489,21 +1417,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
14891417
; GFX1032DAGISEL-LABEL: divergent_value_i64:
14901418
; GFX1032DAGISEL: ; %bb.0: ; %entry
14911419
; GFX1032DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1492-
<<<<<<< HEAD
1493-
<<<<<<< HEAD
1494-
; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
1495-
; GFX1032DAGISEL-NEXT: s_brev_b32 s5, 1
1496-
; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
1497-
=======
1498-
; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
1499-
; GFX1032DAGISEL-NEXT: s_brev_b32 s5, 1
1500-
; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
1501-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1502-
=======
15031420
; GFX1032DAGISEL-NEXT: s_mov_b32 s4, 0
15041421
; GFX1032DAGISEL-NEXT: s_brev_b32 s5, 1
15051422
; GFX1032DAGISEL-NEXT: s_mov_b32 s6, exec_lo
1506-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
15071423
; GFX1032DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
15081424
; GFX1032DAGISEL-NEXT: s_ff1_i32_b32 s7, s6
15091425
; GFX1032DAGISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1525,21 +1441,9 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
15251441
; GFX1032GISEL-LABEL: divergent_value_i64:
15261442
; GFX1032GISEL: ; %bb.0: ; %entry
15271443
; GFX1032GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1528-
<<<<<<< HEAD
1529-
<<<<<<< HEAD
1530-
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
1531-
; GFX1032GISEL-NEXT: s_brev_b32 s5, 1
1532-
; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
1533-
=======
1534-
; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
1535-
; GFX1032GISEL-NEXT: s_brev_b32 s5, 1
1536-
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
1537-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1538-
=======
15391444
; GFX1032GISEL-NEXT: s_mov_b32 s4, 0
15401445
; GFX1032GISEL-NEXT: s_brev_b32 s5, 1
15411446
; GFX1032GISEL-NEXT: s_mov_b32 s6, exec_lo
1542-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
15431447
; GFX1032GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
15441448
; GFX1032GISEL-NEXT: s_ff1_i32_b32 s7, s6
15451449
; GFX1032GISEL-NEXT: v_mov_b32_e32 v4, s4
@@ -1561,39 +1465,16 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
15611465
; GFX1164DAGISEL-LABEL: divergent_value_i64:
15621466
; GFX1164DAGISEL: ; %bb.0: ; %entry
15631467
; GFX1164DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1564-
<<<<<<< HEAD
1565-
<<<<<<< HEAD
1566-
; GFX1164DAGISEL-NEXT: s_mov_b32 s0, 0
1567-
; GFX1164DAGISEL-NEXT: s_brev_b32 s1, 1
1568-
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
1569-
; GFX1164DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1570-
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1571-
=======
1572-
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
1573-
; GFX1164DAGISEL-NEXT: s_brev_b32 s1, 1
1574-
=======
1575-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
15761468
; GFX1164DAGISEL-NEXT: s_mov_b32 s0, 0
15771469
; GFX1164DAGISEL-NEXT: s_brev_b32 s1, 1
15781470
; GFX1164DAGISEL-NEXT: s_mov_b64 s[2:3], exec
15791471
; GFX1164DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1580-
<<<<<<< HEAD
1581-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1582-
=======
15831472
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1584-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
15851473
; GFX1164DAGISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
15861474
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v4, s0
15871475
; GFX1164DAGISEL-NEXT: v_mov_b32_e32 v5, s1
15881476
; GFX1164DAGISEL-NEXT: v_readlane_b32 s4, v2, s8
15891477
; GFX1164DAGISEL-NEXT: v_readlane_b32 s5, v3, s8
1590-
<<<<<<< HEAD
1591-
<<<<<<< HEAD
1592-
=======
1593-
; GFX1164DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1594-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1595-
=======
1596-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
15971478
; GFX1164DAGISEL-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[4:5]
15981479
; GFX1164DAGISEL-NEXT: s_and_b64 s[6:7], vcc, s[2:3]
15991480
; GFX1164DAGISEL-NEXT: s_bitset0_b64 s[2:3], s8
@@ -1609,39 +1490,16 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
16091490
; GFX1164GISEL-LABEL: divergent_value_i64:
16101491
; GFX1164GISEL: ; %bb.0: ; %entry
16111492
; GFX1164GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1612-
<<<<<<< HEAD
1613-
<<<<<<< HEAD
1614-
; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
1615-
; GFX1164GISEL-NEXT: s_brev_b32 s1, 1
1616-
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
1617-
; GFX1164GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1618-
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1619-
=======
1620-
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
1621-
; GFX1164GISEL-NEXT: s_brev_b32 s1, 1
1622-
=======
1623-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
16241493
; GFX1164GISEL-NEXT: s_mov_b32 s0, 0
16251494
; GFX1164GISEL-NEXT: s_brev_b32 s1, 1
16261495
; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
16271496
; GFX1164GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1628-
<<<<<<< HEAD
1629-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1630-
=======
16311497
; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
1632-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
16331498
; GFX1164GISEL-NEXT: s_ctz_i32_b64 s8, s[2:3]
16341499
; GFX1164GISEL-NEXT: v_mov_b32_e32 v4, s0
16351500
; GFX1164GISEL-NEXT: v_mov_b32_e32 v5, s1
16361501
; GFX1164GISEL-NEXT: v_readlane_b32 s4, v2, s8
16371502
; GFX1164GISEL-NEXT: v_readlane_b32 s5, v3, s8
1638-
<<<<<<< HEAD
1639-
<<<<<<< HEAD
1640-
=======
1641-
; GFX1164GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1642-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1643-
=======
1644-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
16451503
; GFX1164GISEL-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[4:5]
16461504
; GFX1164GISEL-NEXT: s_and_b64 s[6:7], vcc, s[2:3]
16471505
; GFX1164GISEL-NEXT: s_bitset0_b64 s[2:3], s8
@@ -1657,38 +1515,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
16571515
; GFX1132DAGISEL-LABEL: divergent_value_i64:
16581516
; GFX1132DAGISEL: ; %bb.0: ; %entry
16591517
; GFX1132DAGISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1660-
<<<<<<< HEAD
1661-
<<<<<<< HEAD
1662-
; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
1663-
; GFX1132DAGISEL-NEXT: s_brev_b32 s1, 1
1664-
; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
1665-
; GFX1132DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1666-
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1667-
=======
1668-
; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
1669-
; GFX1132DAGISEL-NEXT: s_brev_b32 s1, 1
1670-
=======
1671-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
16721518
; GFX1132DAGISEL-NEXT: s_mov_b32 s0, 0
16731519
; GFX1132DAGISEL-NEXT: s_brev_b32 s1, 1
16741520
; GFX1132DAGISEL-NEXT: s_mov_b32 s2, exec_lo
16751521
; GFX1132DAGISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1676-
<<<<<<< HEAD
1677-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1678-
=======
16791522
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1680-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
16811523
; GFX1132DAGISEL-NEXT: s_ctz_i32_b32 s3, s2
16821524
; GFX1132DAGISEL-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
16831525
; GFX1132DAGISEL-NEXT: v_readlane_b32 s4, v2, s3
16841526
; GFX1132DAGISEL-NEXT: v_readlane_b32 s5, v3, s3
1685-
<<<<<<< HEAD
1686-
<<<<<<< HEAD
1687-
=======
1688-
; GFX1132DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1689-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1690-
=======
1691-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
16921527
; GFX1132DAGISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[4:5]
16931528
; GFX1132DAGISEL-NEXT: s_and_b32 s6, vcc_lo, s2
16941529
; GFX1132DAGISEL-NEXT: s_bitset0_b32 s2, s3
@@ -1703,38 +1538,15 @@ define void @divergent_value_i64(ptr addrspace(1) %out, i64 %id.x) {
17031538
; GFX1132GISEL-LABEL: divergent_value_i64:
17041539
; GFX1132GISEL: ; %bb.0: ; %entry
17051540
; GFX1132GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1706-
<<<<<<< HEAD
1707-
<<<<<<< HEAD
1708-
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
1709-
; GFX1132GISEL-NEXT: s_brev_b32 s1, 1
1710-
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
1711-
; GFX1132GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1712-
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1713-
=======
1714-
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
1715-
; GFX1132GISEL-NEXT: s_brev_b32 s1, 1
1716-
=======
1717-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
17181541
; GFX1132GISEL-NEXT: s_mov_b32 s0, 0
17191542
; GFX1132GISEL-NEXT: s_brev_b32 s1, 1
17201543
; GFX1132GISEL-NEXT: s_mov_b32 s2, exec_lo
17211544
; GFX1132GISEL-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
1722-
<<<<<<< HEAD
1723-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1724-
=======
17251545
; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
1726-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
17271546
; GFX1132GISEL-NEXT: s_ctz_i32_b32 s3, s2
17281547
; GFX1132GISEL-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
17291548
; GFX1132GISEL-NEXT: v_readlane_b32 s4, v2, s3
17301549
; GFX1132GISEL-NEXT: v_readlane_b32 s5, v3, s3
1731-
<<<<<<< HEAD
1732-
<<<<<<< HEAD
1733-
=======
1734-
; GFX1132GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
1735-
>>>>>>> 381cb9fada25 ([AMDGPU] Extending wave reduction intrinsics for `i64` types - 1)
1736-
=======
1737-
>>>>>>> 4d2b4133488e (Using `S_MOV_B64_IMM_PSEUDO` instead of dealing with legality concerns.)
17381550
; GFX1132GISEL-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[4:5]
17391551
; GFX1132GISEL-NEXT: s_and_b32 s6, vcc_lo, s2
17401552
; GFX1132GISEL-NEXT: s_bitset0_b32 s2, s3

0 commit comments

Comments
 (0)