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gandhi56gandhi56
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Improve tests
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4 files changed

+285
-105
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir‎

Lines changed: 112 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,15 @@ body: |
1818
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s16)
1919
; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[ANYEXT]], [[ANYEXT1]]
2020
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[ADD]](s32)
21-
; CHECK-NEXT: S_ENDPGM 0, implicit [[TRUNC2]](s16)
21+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_CONSTANT i16 255
22+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s16) = G_AND [[TRUNC2]], [[C]]
2223
%0:_(s32) = COPY $sgpr0
2324
%1:_(s32) = COPY $sgpr1
2425
%2:_(s16) = G_TRUNC %0
2526
%3:_(s16) = G_TRUNC %1
2627
%4:_(s16) = G_ADD %2, %3
27-
S_ENDPGM 0, implicit %4
28+
%5:_(s16) = G_CONSTANT i16 255
29+
%6:_(s16) = G_AND %4, %5
2830
...
2931

3032
---
@@ -43,13 +45,16 @@ body: |
4345
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
4446
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
4547
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s16) = G_ADD [[COPY2]], [[TRUNC1]]
46-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s16)
48+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_CONSTANT i16 255
49+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
50+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[ADD]], [[COPY3]]
4751
%0:_(s32) = COPY $sgpr0
4852
%1:_(s32) = COPY $vgpr0
4953
%2:_(s16) = G_TRUNC %0
5054
%3:_(s16) = G_TRUNC %1
5155
%4:_(s16) = G_ADD %2, %3
52-
S_ENDPGM 0, implicit %4
56+
%5:_(s16) = G_CONSTANT i16 255
57+
%6:_(s16) = G_AND %4, %5
5358
...
5459

5560
---
@@ -68,13 +73,16 @@ body: |
6873
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
6974
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
7075
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s16) = G_ADD [[TRUNC]], [[COPY2]]
71-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s16)
76+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_CONSTANT i16 255
77+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
78+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[ADD]], [[COPY3]]
7279
%0:_(s32) = COPY $vgpr0
7380
%1:_(s32) = COPY $sgpr0
7481
%2:_(s16) = G_TRUNC %0
7582
%3:_(s16) = G_TRUNC %1
7683
%4:_(s16) = G_ADD %2, %3
77-
S_ENDPGM 0, implicit %4
84+
%5:_(s16) = G_CONSTANT i16 255
85+
%6:_(s16) = G_AND %4, %5
7886
...
7987

8088
---
@@ -92,13 +100,16 @@ body: |
92100
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
93101
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
94102
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s16) = G_ADD [[TRUNC]], [[TRUNC1]]
95-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s16)
103+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_CONSTANT i16 255
104+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
105+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[ADD]], [[COPY2]]
96106
%0:_(s32) = COPY $vgpr0
97107
%1:_(s32) = COPY $vgpr1
98108
%2:_(s16) = G_TRUNC %0
99109
%3:_(s16) = G_TRUNC %1
100110
%4:_(s16) = G_ADD %2, %3
101-
S_ENDPGM 0, implicit %4
111+
%5:_(s16) = G_CONSTANT i16 255
112+
%6:_(s16) = G_AND %4, %5
102113
...
103114

104115
---
@@ -114,11 +125,13 @@ body: |
114125
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
115126
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
116127
; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY]], [[COPY1]]
117-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
128+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
129+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ADD]], [[C]]
118130
%0:_(s32) = COPY $sgpr0
119131
%1:_(s32) = COPY $sgpr1
120132
%2:_(s32) = G_ADD %0, %1
121-
S_ENDPGM 0, implicit %2
133+
%3:_(s32) = G_CONSTANT i32 255
134+
%4:_(s32) = G_AND %2, %3
122135
...
123136

124137
---
@@ -135,11 +148,14 @@ body: |
135148
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
136149
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
137150
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY2]], [[COPY1]]
138-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
151+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
152+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
153+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ADD]], [[COPY3]]
139154
%0:_(s32) = COPY $sgpr0
140155
%1:_(s32) = COPY $vgpr0
141156
%2:_(s32) = G_ADD %0, %1
142-
S_ENDPGM 0, implicit %2
157+
%3:_(s32) = G_CONSTANT i32 255
158+
%4:_(s32) = G_AND %2, %3
143159
...
144160

145161
---
@@ -156,11 +172,14 @@ body: |
156172
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
157173
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
158174
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY]], [[COPY2]]
159-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
175+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
176+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
177+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ADD]], [[COPY3]]
160178
%0:_(s32) = COPY $vgpr0
161179
%1:_(s32) = COPY $sgpr0
162180
%2:_(s32) = G_ADD %0, %1
163-
S_ENDPGM 0, implicit %2
181+
%3:_(s32) = G_CONSTANT i32 255
182+
%4:_(s32) = G_AND %2, %3
164183
...
165184

166185
---
@@ -176,11 +195,14 @@ body: |
176195
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
177196
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
178197
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY]], [[COPY1]]
179-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
198+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
199+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
200+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ADD]], [[COPY2]]
180201
%0:_(s32) = COPY $vgpr0
181202
%1:_(s32) = COPY $vgpr1
182203
%2:_(s32) = G_ADD %0, %1
183-
S_ENDPGM 0, implicit %2
204+
%3:_(s32) = G_CONSTANT i32 255
205+
%4:_(s32) = G_AND %2, %3
184206
...
185207

186208
---
@@ -196,11 +218,13 @@ body: |
196218
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
197219
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
198220
; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s64) = G_ADD [[COPY]], [[COPY1]]
199-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
221+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 255
222+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s64) = G_AND [[ADD]], [[C]]
200223
%0:_(s64) = COPY $sgpr0_sgpr1
201224
%1:_(s64) = COPY $sgpr2_sgpr3
202225
%2:_(s64) = G_ADD %0, %1
203-
S_ENDPGM 0, implicit %2
226+
%3:_(s64) = G_CONSTANT i64 255
227+
%4:_(s64) = G_AND %2, %3
204228
...
205229

206230
---
@@ -217,11 +241,18 @@ body: |
217241
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
218242
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
219243
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s64) = G_ADD [[COPY2]], [[COPY1]]
220-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
244+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 255
245+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
246+
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
247+
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
248+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UV]], [[UV2]]
249+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]]
250+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
221251
%0:_(s64) = COPY $sgpr0_sgpr1
222252
%1:_(s64) = COPY $vgpr0_vgpr1
223253
%2:_(s64) = G_ADD %0, %1
224-
S_ENDPGM 0, implicit %2
254+
%3:_(s64) = G_CONSTANT i64 255
255+
%4:_(s64) = G_AND %2, %3
225256
...
226257

227258
---
@@ -238,11 +269,18 @@ body: |
238269
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
239270
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
240271
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s64) = G_ADD [[COPY]], [[COPY2]]
241-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
272+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 255
273+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
274+
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
275+
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](s64)
276+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UV]], [[UV2]]
277+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]]
278+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
242279
%0:_(s64) = COPY $vgpr0_vgpr1
243280
%1:_(s64) = COPY $sgpr0_sgpr1
244281
%2:_(s64) = G_ADD %0, %1
245-
S_ENDPGM 0, implicit %2
282+
%3:_(s64) = G_CONSTANT i64 255
283+
%4:_(s64) = G_AND %2, %3
246284
...
247285

248286
---
@@ -258,11 +296,18 @@ body: |
258296
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
259297
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
260298
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s64) = G_ADD [[COPY]], [[COPY1]]
261-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
299+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 255
300+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
301+
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
302+
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](s64)
303+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UV]], [[UV2]]
304+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]]
305+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
262306
%0:_(s64) = COPY $vgpr0_vgpr1
263307
%1:_(s64) = COPY $vgpr2_vgpr3
264308
%2:_(s64) = G_ADD %0, %1
265-
S_ENDPGM 0, implicit %2
309+
%3:_(s64) = G_CONSTANT i64 255
310+
%4:_(s64) = G_AND %2, %3
266311
...
267312

268313
---
@@ -278,11 +323,13 @@ body: |
278323
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
279324
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
280325
; CHECK-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[COPY]], [[COPY1]]
281-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
326+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
327+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[UADDO]], [[C]]
282328
%0:_(s32) = COPY $sgpr0
283329
%1:_(s32) = COPY $sgpr1
284330
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
285-
S_ENDPGM 0, implicit %2
331+
%4:_(s32) = G_CONSTANT i32 255
332+
%5:_(s32) = G_AND %2, %4
286333
...
287334

288335
---
@@ -299,11 +346,14 @@ body: |
299346
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
300347
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
301348
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY2]], [[COPY1]]
302-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
349+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
350+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
351+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDO]], [[COPY3]]
303352
%0:_(s32) = COPY $sgpr0
304353
%1:_(s32) = COPY $vgpr1
305354
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
306-
S_ENDPGM 0, implicit %2
355+
%4:_(s32) = G_CONSTANT i32 255
356+
%5:_(s32) = G_AND %2, %4
307357
...
308358

309359
---
@@ -320,11 +370,14 @@ body: |
320370
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
321371
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
322372
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY]], [[COPY2]]
323-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
373+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
374+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
375+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDO]], [[COPY3]]
324376
%0:_(s32) = COPY $vgpr0
325377
%1:_(s32) = COPY $sgpr1
326378
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
327-
S_ENDPGM 0, implicit %2
379+
%4:_(s32) = G_CONSTANT i32 255
380+
%5:_(s32) = G_AND %2, %4
328381
...
329382

330383
---
@@ -340,11 +393,14 @@ body: |
340393
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
341394
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
342395
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY]], [[COPY1]]
343-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
396+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
397+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
398+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDO]], [[COPY2]]
344399
%0:_(s32) = COPY $vgpr0
345400
%1:_(s32) = COPY $vgpr1
346401
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
347-
S_ENDPGM 0, implicit %2
402+
%4:_(s32) = G_CONSTANT i32 255
403+
%5:_(s32) = G_AND %2, %4
348404
...
349405

350406
---
@@ -363,13 +419,15 @@ body: |
363419
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
364420
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[C]]
365421
; CHECK-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
366-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
422+
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
423+
; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[UADDE]], [[C1]]
367424
%0:_(s32) = COPY $sgpr0
368425
%1:_(s32) = COPY $sgpr1
369426
%2:_(s32) = COPY $sgpr2
370427
%3:_(s1) = G_TRUNC %2
371428
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
372-
S_ENDPGM 0, implicit %4
429+
%6:_(s32) = G_CONSTANT i32 255
430+
%7:_(s32) = G_AND %4, %6
373431
...
374432

375433
---
@@ -388,13 +446,16 @@ body: |
388446
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
389447
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32)
390448
; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY1]], [[AMDGPU_COPY_VCC_SCC]]
391-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
449+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
450+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
451+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDE]], [[COPY4]]
392452
%0:_(s32) = COPY $sgpr0
393453
%1:_(s32) = COPY $vgpr1
394454
%2:_(s32) = COPY $sgpr2
395455
%3:_(s1) = G_TRUNC %2
396456
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
397-
S_ENDPGM 0, implicit %4
457+
%6:_(s32) = G_CONSTANT i32 255
458+
%7:_(s32) = G_AND %4, %6
398459
...
399460

400461
---
@@ -413,13 +474,16 @@ body: |
413474
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
414475
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32)
415476
; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[AMDGPU_COPY_VCC_SCC]]
416-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
477+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
478+
; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
479+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDE]], [[COPY4]]
417480
%0:_(s32) = COPY $vgpr0
418481
%1:_(s32) = COPY $sgpr1
419482
%2:_(s32) = COPY $sgpr2
420483
%3:_(s1) = G_TRUNC %2
421484
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
422-
S_ENDPGM 0, implicit %4
485+
%6:_(s32) = G_CONSTANT i32 255
486+
%7:_(s32) = G_AND %4, %6
423487
...
424488

425489
---
@@ -440,13 +504,16 @@ body: |
440504
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
441505
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
442506
; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
443-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
507+
; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
508+
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
509+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UADDE]], [[COPY3]]
444510
%0:_(s32) = COPY $vgpr0
445511
%1:_(s32) = COPY $vgpr1
446512
%2:_(s32) = COPY $vgpr2
447513
%3:_(s1) = G_TRUNC %2
448514
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
449-
S_ENDPGM 0, implicit %4
515+
%6:_(s32) = G_CONSTANT i32 255
516+
%7:_(s32) = G_AND %4, %6
450517
...
451518

452519
---
@@ -465,12 +532,14 @@ body: |
465532
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
466533
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[C]]
467534
; CHECK-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
468-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
535+
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 255
536+
; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[UADDE]], [[C1]]
469537
%0:_(s32) = COPY $sgpr0
470538
%1:_(s32) = COPY $sgpr1
471539
%2:_(s32) = COPY $sgpr2
472540
%3:_(s1) = G_TRUNC %2
473541
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
474-
%6:_(s32) = G_ANYEXT %5:_(s1)
475-
S_ENDPGM 0, implicit %4
542+
%6:_(s32) = G_ANYEXT %5
543+
%7:_(s32) = G_CONSTANT i32 255
544+
%8:_(s32) = G_AND %4, %7
476545
...

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