Fix clobbering value for reg += fi case

Author: arsenm

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

@@ -2447,12 +2447,17 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
 
       // Do an in-place scale of the wave offset to the lane offset.
       if (FrameReg && !ST.enableFlatScratch()) {
+        // FIXME: In the common case where the add does not also read its result
+        // (i.e. this isn't a reg += fi), it's not finding the dest reg as
+        // available.
+        Register TmpReg = RS->scavengeRegisterBackwards(
+            AMDGPU::SReg_32_XM0RegClass, MI, false, 0);
         BuildMI(*MBB, *MI, DL, TII->get(AMDGPU::S_LSHR_B32))
-            .addDef(DstOp.getReg(), RegState::Renamable)
+            .addDef(TmpReg, RegState::Renamable)
             .addReg(FrameReg)
             .addImm(ST.getWavefrontSizeLog2())
             .setOperandDead(3); // Set SCC dead
-        MaterializedReg = DstOp.getReg();
+        MaterializedReg = TmpReg;
       }
 
       // If we can't fold the other operand, do another increment.