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[NFC][RISCV] Keep AVLReg define instr inside VSETVLInfo (#89180)
Currently, the vsetvli pass tracks the define instruction through `MRI->getVRegDef` due to the SSA form. This patch keeps the AVLReg DefMI within VSETVLInfo during construction. And replace `MRI->getVRegDef(AVLReg)` with `getAVLRegDefMI()`. This information is useful when vsetvli pass live in post-ra situation. The testcases don't change because the VReg always has a unique def in SSA.
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‎llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp‎

Lines changed: 48 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
156156
}
157157
}
158158

159-
static bool isNonZeroLoadImmediate(MachineInstr &MI) {
159+
static bool isNonZeroLoadImmediate(const MachineInstr &MI) {
160160
return MI.getOpcode() == RISCV::ADDI &&
161161
MI.getOperand(1).isReg() && MI.getOperand(2).isImm() &&
162162
MI.getOperand(1).getReg() == RISCV::X0 &&
@@ -454,8 +454,12 @@ DemandedFields getDemanded(const MachineInstr &MI,
454454
/// Defines the abstract state with which the forward dataflow models the
455455
/// values of the VL and VTYPE registers after insertion.
456456
class VSETVLIInfo {
457+
struct AVLDef {
458+
const MachineInstr *DefMI;
459+
Register DefReg;
460+
};
457461
union {
458-
Register AVLReg;
462+
AVLDef AVLRegDef;
459463
unsigned AVLImm;
460464
};
461465

@@ -490,9 +494,10 @@ class VSETVLIInfo {
490494
void setUnknown() { State = Unknown; }
491495
bool isUnknown() const { return State == Unknown; }
492496

493-
void setAVLReg(Register Reg) {
494-
assert(Reg.isVirtual());
495-
AVLReg = Reg;
497+
void setAVLRegDef(const MachineInstr *DefMI, Register AVLReg) {
498+
assert(DefMI && AVLReg.isVirtual());
499+
AVLRegDef.DefMI = DefMI;
500+
AVLRegDef.DefReg = AVLReg;
496501
State = AVLIsReg;
497502
}
498503

@@ -510,20 +515,24 @@ class VSETVLIInfo {
510515
bool hasAVLVLMAX() const { return State == AVLIsVLMAX; }
511516
bool hasAVLIgnored() const { return State == AVLIsIgnored; }
512517
Register getAVLReg() const {
513-
assert(hasAVLReg());
514-
return AVLReg;
518+
assert(hasAVLReg() && AVLRegDef.DefReg.isVirtual());
519+
return AVLRegDef.DefReg;
515520
}
516521
unsigned getAVLImm() const {
517522
assert(hasAVLImm());
518523
return AVLImm;
519524
}
525+
const MachineInstr &getAVLDefMI() const {
526+
assert(hasAVLReg() && AVLRegDef.DefMI);
527+
return *AVLRegDef.DefMI;
528+
}
520529

521530
void setAVL(VSETVLIInfo Info) {
522531
assert(Info.isValid());
523532
if (Info.isUnknown())
524533
setUnknown();
525534
else if (Info.hasAVLReg())
526-
setAVLReg(Info.getAVLReg());
535+
setAVLRegDef(&Info.getAVLDefMI(), Info.getAVLReg());
527536
else if (Info.hasAVLVLMAX())
528537
setAVLVLMAX();
529538
else if (Info.hasAVLIgnored())
@@ -539,31 +548,28 @@ class VSETVLIInfo {
539548
bool getTailAgnostic() const { return TailAgnostic; }
540549
bool getMaskAgnostic() const { return MaskAgnostic; }
541550

542-
bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const {
551+
bool hasNonZeroAVL() const {
543552
if (hasAVLImm())
544553
return getAVLImm() > 0;
545-
if (hasAVLReg()) {
546-
MachineInstr *MI = MRI.getUniqueVRegDef(getAVLReg());
547-
assert(MI);
548-
return isNonZeroLoadImmediate(*MI);
549-
}
554+
if (hasAVLReg())
555+
return isNonZeroLoadImmediate(getAVLDefMI());
550556
if (hasAVLVLMAX())
551557
return true;
552558
if (hasAVLIgnored())
553559
return false;
554560
return false;
555561
}
556562

557-
bool hasEquallyZeroAVL(const VSETVLIInfo &Other,
558-
const MachineRegisterInfo &MRI) const {
563+
bool hasEquallyZeroAVL(const VSETVLIInfo &Other) const {
559564
if (hasSameAVL(Other))
560565
return true;
561-
return (hasNonZeroAVL(MRI) && Other.hasNonZeroAVL(MRI));
566+
return (hasNonZeroAVL() && Other.hasNonZeroAVL());
562567
}
563568

564569
bool hasSameAVL(const VSETVLIInfo &Other) const {
565570
if (hasAVLReg() && Other.hasAVLReg())
566-
return getAVLReg() == Other.getAVLReg();
571+
return getAVLDefMI().isIdenticalTo(Other.getAVLDefMI()) &&
572+
getAVLReg() == Other.getAVLReg();
567573

568574
if (hasAVLImm() && Other.hasAVLImm())
569575
return getAVLImm() == Other.getAVLImm();
@@ -659,7 +665,7 @@ class VSETVLIInfo {
659665
if (Used.VLAny && !(hasSameAVL(Require) && hasSameVLMAX(Require)))
660666
return false;
661667

662-
if (Used.VLZeroness && !hasEquallyZeroAVL(Require, MRI))
668+
if (Used.VLZeroness && !hasEquallyZeroAVL(Require))
663669
return false;
664670

665671
return hasCompatibleVTYPE(Used, Require);
@@ -744,7 +750,7 @@ class VSETVLIInfo {
744750
if (isUnknown())
745751
OS << "unknown";
746752
if (hasAVLReg())
747-
OS << "AVLReg=" << (unsigned)AVLReg;
753+
OS << "AVLReg=" << (unsigned)getAVLReg();
748754
if (hasAVLImm())
749755
OS << "AVLImm=" << (unsigned)AVLImm;
750756
if (hasAVLVLMAX())
@@ -870,7 +876,8 @@ INITIALIZE_PASS(RISCVCoalesceVSETVLI, "riscv-coalesce-vsetvli",
870876

871877
// Return a VSETVLIInfo representing the changes made by this VSETVLI or
872878
// VSETIVLI instruction.
873-
static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
879+
static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI,
880+
const MachineRegisterInfo &MRI) {
874881
VSETVLIInfo NewInfo;
875882
if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
876883
NewInfo.setAVLImm(MI.getOperand(1).getImm());
@@ -883,7 +890,7 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
883890
if (AVLReg == RISCV::X0)
884891
NewInfo.setAVLVLMAX();
885892
else
886-
NewInfo.setAVLReg(AVLReg);
893+
NewInfo.setAVLRegDef(MRI.getVRegDef(AVLReg), AVLReg);
887894
}
888895
NewInfo.setVTYPE(MI.getOperand(2).getImm());
889896

@@ -955,7 +962,7 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
955962
else
956963
InstrInfo.setAVLImm(Imm);
957964
} else {
958-
InstrInfo.setAVLReg(VLOp.getReg());
965+
InstrInfo.setAVLRegDef(MRI->getVRegDef(VLOp.getReg()), VLOp.getReg());
959966
}
960967
} else {
961968
assert(isScalarExtractInstr(MI));
@@ -976,10 +983,9 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
976983
// register AVLs to avoid extending live ranges without being sure we can
977984
// kill the original source reg entirely.
978985
if (InstrInfo.hasAVLReg()) {
979-
MachineInstr *DefMI = MRI->getUniqueVRegDef(InstrInfo.getAVLReg());
980-
assert(DefMI);
981-
if (isVectorConfigInstr(*DefMI)) {
982-
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI);
986+
const MachineInstr &DefMI = InstrInfo.getAVLDefMI();
987+
if (isVectorConfigInstr(DefMI)) {
988+
VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(DefMI, *MRI);
983989
if (DefInstrInfo.hasSameVLMAX(InstrInfo) &&
984990
(DefInstrInfo.hasAVLImm() || DefInstrInfo.hasAVLVLMAX()))
985991
InstrInfo.setAVL(DefInstrInfo);
@@ -1017,10 +1023,9 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
10171023
// it has the same VLMAX we want and the last VL/VTYPE we observed is the
10181024
// same, we can use the X0, X0 form.
10191025
if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) {
1020-
MachineInstr *DefMI = MRI->getUniqueVRegDef(Info.getAVLReg());
1021-
assert(DefMI);
1022-
if (isVectorConfigInstr(*DefMI)) {
1023-
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
1026+
const MachineInstr &DefMI = Info.getAVLDefMI();
1027+
if (isVectorConfigInstr(DefMI)) {
1028+
VSETVLIInfo DefInfo = getInfoForVSETVLI(DefMI, *MRI);
10241029
if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) {
10251030
BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0))
10261031
.addReg(RISCV::X0, RegState::Define | RegState::Dead)
@@ -1136,10 +1141,9 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
11361141
// and the last VL/VTYPE we observed is the same, we don't need a
11371142
// VSETVLI here.
11381143
if (Require.hasAVLReg() && CurInfo.hasCompatibleVTYPE(Used, Require)) {
1139-
MachineInstr *DefMI = MRI->getUniqueVRegDef(Require.getAVLReg());
1140-
assert(DefMI);
1141-
if (isVectorConfigInstr(*DefMI)) {
1142-
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
1144+
const MachineInstr &DefMI = Require.getAVLDefMI();
1145+
if (isVectorConfigInstr(DefMI)) {
1146+
VSETVLIInfo DefInfo = getInfoForVSETVLI(DefMI, *MRI);
11431147
if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo))
11441148
return false;
11451149
}
@@ -1194,7 +1198,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
11941198
// variant, so we avoid the transform to prevent extending live range of an
11951199
// avl register operand.
11961200
// TODO: We can probably relax this for immediates.
1197-
bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo, *MRI) &&
1201+
bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo) &&
11981202
IncomingInfo.hasSameVLMAX(PrevInfo);
11991203
if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero))
12001204
Info.setAVL(IncomingInfo);
@@ -1225,13 +1229,14 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
12251229
void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
12261230
const MachineInstr &MI) const {
12271231
if (isVectorConfigInstr(MI)) {
1228-
Info = getInfoForVSETVLI(MI);
1232+
Info = getInfoForVSETVLI(MI, *MRI);
12291233
return;
12301234
}
12311235

12321236
if (RISCV::isFaultFirstLoad(MI)) {
12331237
// Update AVL to vl-output of the fault first load.
1234-
Info.setAVLReg(MI.getOperand(1).getReg());
1238+
Info.setAVLRegDef(MRI->getVRegDef(MI.getOperand(1).getReg()),
1239+
MI.getOperand(1).getReg());
12351240
return;
12361241
}
12371242

@@ -1325,11 +1330,8 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
13251330
if (!Require.hasAVLReg())
13261331
return true;
13271332

1328-
Register AVLReg = Require.getAVLReg();
1329-
13301333
// We need the AVL to be produce by a PHI node in this basic block.
1331-
MachineInstr *PHI = MRI->getUniqueVRegDef(AVLReg);
1332-
assert(PHI);
1334+
const MachineInstr *PHI = &Require.getAVLDefMI();
13331335
if (PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB)
13341336
return true;
13351337

@@ -1346,7 +1348,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
13461348

13471349
// We found a VSET(I)VLI make sure it matches the output of the
13481350
// predecessor block.
1349-
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI);
1351+
VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI, *MRI);
13501352
if (DefInfo != PBBExit)
13511353
return true;
13521354

@@ -1500,8 +1502,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
15001502
// we need to prove the value is available at the point we're going
15011503
// to insert the vsetvli at.
15021504
if (AvailableInfo.hasAVLReg()) {
1503-
MachineInstr *AVLDefMI = MRI->getUniqueVRegDef(AvailableInfo.getAVLReg());
1504-
assert(AVLDefMI);
1505+
const MachineInstr *AVLDefMI = &AvailableInfo.getAVLDefMI();
15051506
// This is an inline dominance check which covers the case of
15061507
// UnavailablePred being the preheader of a loop.
15071508
if (AVLDefMI->getParent() != UnavailablePred)
@@ -1580,8 +1581,8 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI,
15801581
if (Used.VLZeroness) {
15811582
if (isVLPreservingConfig(PrevMI))
15821583
return false;
1583-
if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI),
1584-
MRI))
1584+
if (!getInfoForVSETVLI(PrevMI, MRI)
1585+
.hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI)))
15851586
return false;
15861587
}
15871588

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