[𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.6-beta.1

[skip ci]

Author: Prabhuk

llvm/test/CodeGen/AArch64/calleetypeid-directcall-mismatched.ll

@@ -5,8 +5,11 @@
 ; Function Attrs: mustprogress noinline optnone uwtable
 define i32 @_Z3fooiii(i32 %x, i32 %y, i32 %z) !type !3 {
 entry:
-  ; CHECK: callSites:
-  ; CHECK-NOT: calleeTypeIds:  
+  ;; Test that `calleeTypeIds` field is not present in `callSites`
+  ; CHECK-LABEL: callSites:
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
   %x.addr = alloca i32, align 4
   %y.addr = alloca i32, align 4
   %z.addr = alloca i32, align 4

llvm/test/CodeGen/ARM/calleetypeid-directcall-mismatched.ll

@@ -5,8 +5,11 @@
 ; Function Attrs: mustprogress noinline optnone uwtable
 define i32 @_Z3fooiii(i32 %x, i32 %y, i32 %z) !type !3 {
 entry:
-  ; CHECK: callSites:
-  ; CHECK-NOT: calleeTypeIds:  
+  ;; Test that `calleeTypeIds` field is not present in `callSites`
+  ; CHECK-LABEL: callSites:
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
   %x.addr = alloca i32, align 4
   %y.addr = alloca i32, align 4
   %z.addr = alloca i32, align 4

llvm/test/CodeGen/Mips/calleetypeid-directcall-mismatched.ll

@@ -5,8 +5,11 @@
 ; Function Attrs: mustprogress noinline optnone uwtable
 define i32 @_Z3fooiii(i32 %x, i32 %y, i32 %z) !type !3 {
 entry:
-  ; CHECK: callSites:
-  ; CHECK-NOT: calleeTypeIds:  
+  ;; Test that `calleeTypeIds` field is not present in `callSites`
+  ; CHECK-LABEL: callSites:
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
   %x.addr = alloca i32, align 4
   %y.addr = alloca i32, align 4
   %z.addr = alloca i32, align 4

llvm/test/CodeGen/RISCV/calleetypeid-directcall-mismatched.ll

@@ -6,8 +6,11 @@
 ; Function Attrs: mustprogress noinline optnone uwtable
 define i32 @_Z3fooiii(i32 %x, i32 %y, i32 %z) !type !3 {
 entry:
-  ; CHECK: callSites:
-  ; CHECK-NOT: calleeTypeIds:  
+  ;; Test that `calleeTypeIds` field is not present in `callSites`
+  ; CHECK-LABEL: callSites:
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
   %x.addr = alloca i32, align 4
   %y.addr = alloca i32, align 4
   %z.addr = alloca i32, align 4

llvm/test/CodeGen/X86/calleetypeid-directcall-mismatched.ll

@@ -5,8 +5,11 @@
 ; Function Attrs: mustprogress noinline optnone uwtable
 define i32 @_Z3fooiii(i32 %x, i32 %y, i32 %z) !type !3 {
 entry:
-  ; CHECK: callSites:
-  ; CHECK-NOT: calleeTypeIds:  
+  ;; Test that `calleeTypeIds` field is not present in `callSites`
+  ; CHECK-LABEL: callSites:
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
+  ; CHECK-NEXT: - { bb: {{[0-9]+}}, offset: {{[0-9]+}}, fwdArgRegs: [] }
   %x.addr = alloca i32, align 4
   %y.addr = alloca i32, align 4
   %z.addr = alloca i32, align 4