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Merge branch 'llvm:main' into gh-101657 
2 parents 252e0c0 + a3744f0 commit 585bd72

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‎clang-tools-extra/clangd/unittests/Matchers.h‎

Lines changed: 0 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -127,74 +127,6 @@ PolySubsequenceMatcher<Args...> HasSubsequence(Args &&... M) {
127127
llvm::consumeError(ComputedValue.takeError()); \
128128
} while (false)
129129

130-
// Implements the HasValue(m) matcher for matching an Optional whose
131-
// value matches matcher m.
132-
template <typename InnerMatcher> class OptionalMatcher {
133-
public:
134-
explicit OptionalMatcher(const InnerMatcher &matcher) : matcher_(matcher) {}
135-
OptionalMatcher(const OptionalMatcher&) = default;
136-
OptionalMatcher &operator=(const OptionalMatcher&) = delete;
137-
138-
// This type conversion operator template allows Optional(m) to be
139-
// used as a matcher for any Optional type whose value type is
140-
// compatible with the inner matcher.
141-
//
142-
// The reason we do this instead of relying on
143-
// MakePolymorphicMatcher() is that the latter is not flexible
144-
// enough for implementing the DescribeTo() method of Optional().
145-
template <typename Optional> operator Matcher<Optional>() const {
146-
return MakeMatcher(new Impl<Optional>(matcher_));
147-
}
148-
149-
private:
150-
// The monomorphic implementation that works for a particular optional type.
151-
template <typename Optional>
152-
class Impl : public ::testing::MatcherInterface<Optional> {
153-
public:
154-
using Value = typename std::remove_const<
155-
typename std::remove_reference<Optional>::type>::type::value_type;
156-
157-
explicit Impl(const InnerMatcher &matcher)
158-
: matcher_(::testing::MatcherCast<const Value &>(matcher)) {}
159-
160-
Impl(const Impl&) = default;
161-
Impl &operator=(const Impl&) = delete;
162-
163-
virtual void DescribeTo(::std::ostream *os) const {
164-
*os << "has a value that ";
165-
matcher_.DescribeTo(os);
166-
}
167-
168-
virtual void DescribeNegationTo(::std::ostream *os) const {
169-
*os << "does not have a value that ";
170-
matcher_.DescribeTo(os);
171-
}
172-
173-
virtual bool
174-
MatchAndExplain(Optional optional,
175-
::testing::MatchResultListener *listener) const {
176-
if (!optional)
177-
return false;
178-
179-
*listener << "which has a value ";
180-
return MatchPrintAndExplain(*optional, matcher_, listener);
181-
}
182-
183-
private:
184-
const Matcher<const Value &> matcher_;
185-
};
186-
187-
const InnerMatcher matcher_;
188-
};
189-
190-
// Creates a matcher that matches an Optional that has a value
191-
// that matches inner_matcher.
192-
template <typename InnerMatcher>
193-
inline OptionalMatcher<InnerMatcher>
194-
HasValue(const InnerMatcher &inner_matcher) {
195-
return OptionalMatcher<InnerMatcher>(inner_matcher);
196-
}
197-
198130
} // namespace clangd
199131
} // namespace clang
200132
#endif

‎clang-tools-extra/clangd/unittests/TypeHierarchyTests.cpp‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ using ::testing::ElementsAre;
2828
using ::testing::Field;
2929
using ::testing::IsEmpty;
3030
using ::testing::Matcher;
31+
using ::testing::Optional;
3132
using ::testing::SizeIs;
3233
using ::testing::UnorderedElementsAre;
3334

@@ -38,12 +39,12 @@ MATCHER_P(selectionRangeIs, R, "") { return arg.selectionRange == R; }
3839
template <class... ParentMatchers>
3940
::testing::Matcher<TypeHierarchyItem> parents(ParentMatchers... ParentsM) {
4041
return Field(&TypeHierarchyItem::parents,
41-
HasValue(UnorderedElementsAre(ParentsM...)));
42+
Optional(UnorderedElementsAre(ParentsM...)));
4243
}
4344
template <class... ChildMatchers>
4445
::testing::Matcher<TypeHierarchyItem> children(ChildMatchers... ChildrenM) {
4546
return Field(&TypeHierarchyItem::children,
46-
HasValue(UnorderedElementsAre(ChildrenM...)));
47+
Optional(UnorderedElementsAre(ChildrenM...)));
4748
}
4849
// Note: "not resolved" is different from "resolved but empty"!
4950
MATCHER(parentsNotResolved, "") { return !arg.parents; }
@@ -790,7 +791,7 @@ struct Child : Parent1, Parent2 {};
790791
Children,
791792
UnorderedElementsAre(
792793
AllOf(withName("Child"),
793-
withResolveParents(HasValue(UnorderedElementsAre(withResolveID(
794+
withResolveParents(Optional(UnorderedElementsAre(withResolveID(
794795
getSymbolID(&findDecl(AST, "Parent1")).str())))))));
795796
}
796797

@@ -810,9 +811,9 @@ struct Chil^d : Parent {};
810811
ASSERT_THAT(Result, SizeIs(1));
811812
auto Parents = superTypes(Result.front(), Index.get());
812813

813-
EXPECT_THAT(Parents, HasValue(UnorderedElementsAre(
814+
EXPECT_THAT(Parents, Optional(UnorderedElementsAre(
814815
AllOf(withName("Parent"),
815-
withResolveParents(HasValue(IsEmpty()))))));
816+
withResolveParents(Optional(IsEmpty()))))));
816817
}
817818
} // namespace
818819
} // namespace clangd

‎clang/include/clang/Basic/arm_immcheck_incl.td‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,18 +2,20 @@ class ImmCheckType<int val> {
22
int Value = val;
33
}
44

5-
// These must be kept in sync with the flags in include/clang/Basic/TargetBuiltins.h
5+
6+
// For SVE, container_size refers to the width of a vector segment (128b).
7+
// For NEON, container_size refers to the vector width (64b or 128b).
68
def ImmCheck0_31 : ImmCheckType<0>; // 0..31 (used for e.g. predicate patterns)
79
def ImmCheck1_16 : ImmCheckType<1>; // 1..16
810
def ImmCheckExtract : ImmCheckType<2>; // 0..(2048/sizeinbits(elt) - 1)
911
def ImmCheckShiftRight : ImmCheckType<3>; // 1..sizeinbits(elt)
1012
def ImmCheckShiftRightNarrow : ImmCheckType<4>; // 1..sizeinbits(elt)/2
1113
def ImmCheckShiftLeft : ImmCheckType<5>; // 0..(sizeinbits(elt) - 1)
1214
def ImmCheck0_7 : ImmCheckType<6>; // 0..7
13-
def ImmCheckLaneIndex : ImmCheckType<7>; // 0..(sizeinbits(vec)/(sizeinbits(elt)) - 1)
15+
def ImmCheckLaneIndex : ImmCheckType<7>; // 0..(container_size/(sizeinbits(elt)) - 1)
1416
def ImmCheckCvt : ImmCheckType<8>; // 1..sizeinbits(elt) (same as ShiftRight)
15-
def ImmCheckLaneIndexCompRotate : ImmCheckType<9>; // 0..(sizeinbits(vec)/(2*sizeinbits(elt)) - 1)
16-
def ImmCheckLaneIndexDot : ImmCheckType<10>; // 0..(sizeinbits(vec)/(4*sizeinbits(elt)) - 1)
17+
def ImmCheckLaneIndexCompRotate : ImmCheckType<9>; // 0..(container_size/(2*sizeinbits(elt)) - 1)
18+
def ImmCheckLaneIndexDot : ImmCheckType<10>; // 0..(container_size/(4*sizeinbits(elt)) - 1)
1719
def ImmCheckComplexRot90_270 : ImmCheckType<11>; // [90,270]
1820
def ImmCheckComplexRotAll90 : ImmCheckType<12>; // [0, 90, 180,270]
1921
def ImmCheck0_13 : ImmCheckType<13>; // 0..13

‎clang/lib/AST/ByteCode/InterpBuiltin.cpp‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1863,6 +1863,10 @@ static bool interp__builtin_memcpy(InterpState &S, CodePtr OpPC,
18631863
return false;
18641864
}
18651865

1866+
// Can't read from dummy pointers.
1867+
if (DestPtr.isDummy() || SrcPtr.isDummy())
1868+
return false;
1869+
18661870
QualType DestElemType;
18671871
size_t RemainingDestElems;
18681872
if (DestPtr.getFieldDesc()->isArray()) {
@@ -1925,9 +1929,6 @@ static bool interp__builtin_memcpy(InterpState &S, CodePtr OpPC,
19251929
}
19261930
}
19271931

1928-
// As a last resort, reject dummy pointers.
1929-
if (DestPtr.isDummy() || SrcPtr.isDummy())
1930-
return false;
19311932
assert(Size.getZExtValue() % DestElemSize == 0);
19321933
if (!DoMemcpy(S, OpPC, SrcPtr, DestPtr, Bytes(Size.getZExtValue()).toBits()))
19331934
return false;

‎clang/lib/Sema/SemaARM.cpp‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -372,7 +372,7 @@ enum ArmSMEState : unsigned {
372372

373373
bool SemaARM::CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy,
374374
unsigned ArgIdx, unsigned EltBitWidth,
375-
unsigned VecBitWidth) {
375+
unsigned ContainerBitWidth) {
376376
// Function that checks whether the operand (ArgIdx) is an immediate
377377
// that is one of a given set of values.
378378
auto CheckImmediateInSet = [&](std::initializer_list<int64_t> Set,
@@ -445,17 +445,17 @@ bool SemaARM::CheckImmediateArg(CallExpr *TheCall, unsigned CheckTy,
445445
break;
446446
case ImmCheckType::ImmCheckLaneIndex:
447447
if (SemaRef.BuiltinConstantArgRange(TheCall, ArgIdx, 0,
448-
(VecBitWidth / EltBitWidth) - 1))
448+
(ContainerBitWidth / EltBitWidth) - 1))
449449
return true;
450450
break;
451451
case ImmCheckType::ImmCheckLaneIndexCompRotate:
452-
if (SemaRef.BuiltinConstantArgRange(TheCall, ArgIdx, 0,
453-
(VecBitWidth / (2 * EltBitWidth)) - 1))
452+
if (SemaRef.BuiltinConstantArgRange(
453+
TheCall, ArgIdx, 0, (ContainerBitWidth / (2 * EltBitWidth)) - 1))
454454
return true;
455455
break;
456456
case ImmCheckType::ImmCheckLaneIndexDot:
457-
if (SemaRef.BuiltinConstantArgRange(TheCall, ArgIdx, 0,
458-
(VecBitWidth / (4 * EltBitWidth)) - 1))
457+
if (SemaRef.BuiltinConstantArgRange(
458+
TheCall, ArgIdx, 0, (ContainerBitWidth / (4 * EltBitWidth)) - 1))
459459
return true;
460460
break;
461461
case ImmCheckType::ImmCheckComplexRot90_270:
@@ -515,13 +515,13 @@ bool SemaARM::PerformNeonImmChecks(
515515
bool HasError = false;
516516

517517
for (const auto &I : ImmChecks) {
518-
auto [ArgIdx, CheckTy, ElementSizeInBits, VecSizeInBits] = I;
518+
auto [ArgIdx, CheckTy, ElementBitWidth, VecBitWidth] = I;
519519

520520
if (OverloadType >= 0)
521-
ElementSizeInBits = NeonTypeFlags(OverloadType).getEltSizeInBits();
521+
ElementBitWidth = NeonTypeFlags(OverloadType).getEltSizeInBits();
522522

523-
HasError |= CheckImmediateArg(TheCall, CheckTy, ArgIdx, ElementSizeInBits,
524-
VecSizeInBits);
523+
HasError |= CheckImmediateArg(TheCall, CheckTy, ArgIdx, ElementBitWidth,
524+
VecBitWidth);
525525
}
526526

527527
return HasError;
@@ -532,9 +532,9 @@ bool SemaARM::PerformSVEImmChecks(
532532
bool HasError = false;
533533

534534
for (const auto &I : ImmChecks) {
535-
auto [ArgIdx, CheckTy, ElementSizeInBits] = I;
535+
auto [ArgIdx, CheckTy, ElementBitWidth] = I;
536536
HasError |=
537-
CheckImmediateArg(TheCall, CheckTy, ArgIdx, ElementSizeInBits, 128);
537+
CheckImmediateArg(TheCall, CheckTy, ArgIdx, ElementBitWidth, 128);
538538
}
539539

540540
return HasError;

‎clang/test/CodeGen/builtin-memfns.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
// RUN: %clang_cc1 -triple i386-pc-linux-gnu -emit-llvm < %s| FileCheck %s
2+
// RUN: %clang_cc1 -triple i386-pc-linux-gnu -emit-llvm -fexperimental-new-constant-interpreter < %s| FileCheck %s
23

34
typedef __WCHAR_TYPE__ wchar_t;
45
typedef __SIZE_TYPE__ size_t;

‎llvm/test/Analysis/CostModel/AArch64/shuffle-select.ll‎

Lines changed: 69 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -1,97 +1,112 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 5
12
; RUN: opt < %s -mtriple=aarch64--linux-gnu -passes="print<cost-model>" 2>&1 -disable-output | FileCheck %s --check-prefix=COST
2-
; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s --check-prefix=CODE
33

44
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
55

6-
; COST-LABEL: sel.v8i8
7-
; COST: Found an estimated cost of 28 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
8-
; CODE-LABEL: sel.v8i8
9-
; CODE: tbl v0.8b, { v0.16b }, v1.8b
10-
define <8 x i8> @sel.v8i8(<8 x i8> %v0, <8 x i8> %v1) {
6+
define <8 x i8> @sel_v8i8(<8 x i8> %v0, <8 x i8> %v1) {
7+
; COST-LABEL: 'sel_v8i8'
8+
; COST-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
9+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i8> %tmp0
10+
;
1111
%tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
1212
ret <8 x i8> %tmp0
1313
}
1414

15-
; COST-LABEL: sel.v16i8
16-
; COST: Found an estimated cost of 60 for instruction: %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
17-
; CODE-LABEL: sel.v16i8
18-
; CODE: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
19-
define <16 x i8> @sel.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
15+
define <16 x i8> @sel_v16i8(<16 x i8> %v0, <16 x i8> %v1) {
16+
; COST-LABEL: 'sel_v16i8'
17+
; COST-NEXT: Cost Model: Found an estimated cost of 60 for instruction: %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
18+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <16 x i8> %tmp0
19+
;
2020
%tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>
2121
ret <16 x i8> %tmp0
2222
}
2323

24-
; COST-LABEL: sel.v4i16
25-
; COST: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x i16> %v0, <4 x i16> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
26-
; CODE-LABEL: sel.v4i16
27-
; CODE: rev32 v0.4h, v0.4h
28-
; CODE: trn2 v0.4h, v0.4h, v1.4h
29-
define <4 x i16> @sel.v4i16(<4 x i16> %v0, <4 x i16> %v1) {
24+
define <4 x i16> @sel_v4i16(<4 x i16> %v0, <4 x i16> %v1) {
25+
; COST-LABEL: 'sel_v4i16'
26+
; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x i16> %v0, <4 x i16> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
27+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i16> %tmp0
28+
;
3029
%tmp0 = shufflevector <4 x i16> %v0, <4 x i16> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
3130
ret <4 x i16> %tmp0
3231
}
3332

34-
; COST-LABEL: sel.v8i16
35-
; COST: Found an estimated cost of 28 for instruction: %tmp0 = shufflevector <8 x i16> %v0, <8 x i16> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
36-
; CODE-LABEL: sel.v8i16
37-
; CODE: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
38-
define <8 x i16> @sel.v8i16(<8 x i16> %v0, <8 x i16> %v1) {
33+
define <8 x i16> @sel_v8i16(<8 x i16> %v0, <8 x i16> %v1) {
34+
; COST-LABEL: 'sel_v8i16'
35+
; COST-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %tmp0 = shufflevector <8 x i16> %v0, <8 x i16> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
36+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x i16> %tmp0
37+
;
3938
%tmp0 = shufflevector <8 x i16> %v0, <8 x i16> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
4039
ret <8 x i16> %tmp0
4140
}
4241

43-
; COST-LABEL: sel.v2i32
44-
; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x i32> %v0, <2 x i32> %v1, <2 x i32> <i32 0, i32 3>
45-
; CODE-LABEL: sel.v2i32
46-
; CODE: mov v0.s[1], v1.s[1]
47-
define <2 x i32> @sel.v2i32(<2 x i32> %v0, <2 x i32> %v1) {
42+
define <2 x i32> @sel_v2i32(<2 x i32> %v0, <2 x i32> %v1) {
43+
; COST-LABEL: 'sel_v2i32'
44+
; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x i32> %v0, <2 x i32> %v1, <2 x i32> <i32 0, i32 3>
45+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i32> %tmp0
46+
;
4847
%tmp0 = shufflevector <2 x i32> %v0, <2 x i32> %v1, <2 x i32> <i32 0, i32 3>
4948
ret <2 x i32> %tmp0
5049
}
5150

52-
; COST-LABEL: sel.v4i32
53-
; COST: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
54-
; CODE-LABEL: sel.v4i32
55-
; CODE: rev64 v0.4s, v0.4s
56-
; CODE: trn2 v0.4s, v0.4s, v1.4s
57-
define <4 x i32> @sel.v4i32(<4 x i32> %v0, <4 x i32> %v1) {
51+
define <4 x i32> @sel_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
52+
; COST-LABEL: 'sel_v4i32'
53+
; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
54+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x i32> %tmp0
55+
;
5856
%tmp0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
5957
ret <4 x i32> %tmp0
6058
}
6159

62-
; COST-LABEL: sel.v2i64
63-
; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x i64> %v0, <2 x i64> %v1, <2 x i32> <i32 0, i32 3>
64-
; CODE-LABEL: sel.v2i64
65-
; CODE: mov v0.d[1], v1.d[1]
66-
define <2 x i64> @sel.v2i64(<2 x i64> %v0, <2 x i64> %v1) {
60+
define <2 x i64> @sel_v2i64(<2 x i64> %v0, <2 x i64> %v1) {
61+
; COST-LABEL: 'sel_v2i64'
62+
; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x i64> %v0, <2 x i64> %v1, <2 x i32> <i32 0, i32 3>
63+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x i64> %tmp0
64+
;
6765
%tmp0 = shufflevector <2 x i64> %v0, <2 x i64> %v1, <2 x i32> <i32 0, i32 3>
6866
ret <2 x i64> %tmp0
6967
}
7068

71-
; COST-LABEL: sel.v2f32
72-
; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x float> %v0, <2 x float> %v1, <2 x i32> <i32 0, i32 3>
73-
; CODE-LABEL: sel.v2f32
74-
; CODE: mov v0.s[1], v1.s[1]
75-
define <2 x float> @sel.v2f32(<2 x float> %v0, <2 x float> %v1) {
69+
define <4 x half> @sel_v4f16(<4 x half> %v0, <4 x half> %v1) {
70+
; COST-LABEL: 'sel_v4f16'
71+
; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x half> %v0, <4 x half> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
72+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x half> %tmp0
73+
;
74+
%tmp0 = shufflevector <4 x half> %v0, <4 x half> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
75+
ret <4 x half> %tmp0
76+
}
77+
78+
define <8 x half> @sel_v8f16(<8 x half> %v0, <8 x half> %v1) {
79+
; COST-LABEL: 'sel_v8f16'
80+
; COST-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %tmp0 = shufflevector <8 x half> %v0, <8 x half> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
81+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <8 x half> %tmp0
82+
;
83+
%tmp0 = shufflevector <8 x half> %v0, <8 x half> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>
84+
ret <8 x half> %tmp0
85+
}
86+
87+
define <2 x float> @sel_v2f32(<2 x float> %v0, <2 x float> %v1) {
88+
; COST-LABEL: 'sel_v2f32'
89+
; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x float> %v0, <2 x float> %v1, <2 x i32> <i32 0, i32 3>
90+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x float> %tmp0
91+
;
7692
%tmp0 = shufflevector <2 x float> %v0, <2 x float> %v1, <2 x i32> <i32 0, i32 3>
7793
ret <2 x float> %tmp0
7894
}
7995

80-
; COST-LABEL: sel.v4f32
81-
; COST: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x float> %v0, <4 x float> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
82-
; CODE-LABEL: sel.v4f32
83-
; CODE: rev64 v0.4s, v0.4s
84-
; CODE: trn2 v0.4s, v0.4s, v1.4s
85-
define <4 x float> @sel.v4f32(<4 x float> %v0, <4 x float> %v1) {
96+
define <4 x float> @sel_v4f32(<4 x float> %v0, <4 x float> %v1) {
97+
; COST-LABEL: 'sel_v4f32'
98+
; COST-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %tmp0 = shufflevector <4 x float> %v0, <4 x float> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
99+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <4 x float> %tmp0
100+
;
86101
%tmp0 = shufflevector <4 x float> %v0, <4 x float> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
87102
ret <4 x float> %tmp0
88103
}
89104

90-
; COST-LABEL: sel.v2f64
91-
; COST: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x double> %v0, <2 x double> %v1, <2 x i32> <i32 0, i32 3>
92-
; CODE-LABEL: sel.v2f64
93-
; CODE: mov v0.d[1], v1.d[1]
94-
define <2 x double> @sel.v2f64(<2 x double> %v0, <2 x double> %v1) {
105+
define <2 x double> @sel_v2f64(<2 x double> %v0, <2 x double> %v1) {
106+
; COST-LABEL: 'sel_v2f64'
107+
; COST-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %tmp0 = shufflevector <2 x double> %v0, <2 x double> %v1, <2 x i32> <i32 0, i32 3>
108+
; COST-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret <2 x double> %tmp0
109+
;
95110
%tmp0 = shufflevector <2 x double> %v0, <2 x double> %v1, <2 x i32> <i32 0, i32 3>
96111
ret <2 x double> %tmp0
97112
}

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