Skip to content

Commit 58df9b1

Browse files
preamespreames
authored
[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)
This block of code is currently conditional on the fusions being enabled but as far as I can tell, does no harm to generally enable. The net effect is the generically compiled code runs slightly better on machines with this fusion. The actual motivation is merely to stop confusing myself when I see the sequence in code; the register allocators choice to sometimes blow two registers instead of one is just generally weird, and my eyes spot it when scanning disassembly. (Note that this is just the regalloc hint; the scheduling changes remain conditional, and probably should remain so.)
1 parent 658a931 commit 58df9b1

17 files changed

+147
-197
lines changed

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -966,17 +966,17 @@ bool RISCVRegisterInfo::getRegAllocationHints(
966966
}
967967
}
968968

969-
// Add a hint if it would allow auipc/lui+addi(w) fusion.
969+
// Add a hint if it would allow auipc/lui+addi(w) fusion. We do this even
970+
// without the fusions explicitly enabled as the impact is rarely negative
971+
// and some cores do implement this fusion.
970972
if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
971973
MI.getOperand(1).isReg()) {
972974
const MachineBasicBlock &MBB = *MI.getParent();
973975
MachineBasicBlock::const_iterator I = MI.getIterator();
974976
// Is the previous instruction a LUI or AUIPC that can be fused?
975977
if (I != MBB.begin()) {
976978
I = skipDebugInstructionsBackward(std::prev(I), MBB.begin());
977-
if (((I->getOpcode() == RISCV::LUI && Subtarget.hasLUIADDIFusion()) ||
978-
(I->getOpcode() == RISCV::AUIPC &&
979-
Subtarget.hasAUIPCADDIFusion())) &&
979+
if ((I->getOpcode() == RISCV::LUI || I->getOpcode() == RISCV::AUIPC) &&
980980
I->getOperand(0).getReg() == MI.getOperand(1).getReg()) {
981981
if (OpIdx == 0)
982982
tryAddHint(MO, MI.getOperand(1), /*NeedGPRC=*/false);

‎llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1155,8 +1155,8 @@ define void @va3_caller() nounwind {
11551155
; RV32: # %bb.0:
11561156
; RV32-NEXT: addi sp, sp, -16
11571157
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1158-
; RV32-NEXT: lui a0, 5
1159-
; RV32-NEXT: addi a3, a0, -480
1158+
; RV32-NEXT: lui a3, 5
1159+
; RV32-NEXT: addi a3, a3, -480
11601160
; RV32-NEXT: li a0, 2
11611161
; RV32-NEXT: li a1, 1111
11621162
; RV32-NEXT: li a2, 0
@@ -1184,8 +1184,8 @@ define void @va3_caller() nounwind {
11841184
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
11851185
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
11861186
; RV32-WITHFP-NEXT: addi s0, sp, 16
1187-
; RV32-WITHFP-NEXT: lui a0, 5
1188-
; RV32-WITHFP-NEXT: addi a3, a0, -480
1187+
; RV32-WITHFP-NEXT: lui a3, 5
1188+
; RV32-WITHFP-NEXT: addi a3, a3, -480
11891189
; RV32-WITHFP-NEXT: li a0, 2
11901190
; RV32-WITHFP-NEXT: li a1, 1111
11911191
; RV32-WITHFP-NEXT: li a2, 0

‎llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -393,8 +393,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
393393
; RV32I-NEXT: # %bb.1: # %cond.false
394394
; RV32I-NEXT: neg a1, a0
395395
; RV32I-NEXT: and a1, a0, a1
396-
; RV32I-NEXT: lui a2, 30667
397-
; RV32I-NEXT: addi s2, a2, 1329
396+
; RV32I-NEXT: lui s2, 30667
397+
; RV32I-NEXT: addi s2, s2, 1329
398398
; RV32I-NEXT: mv s4, a0
399399
; RV32I-NEXT: mv a0, a1
400400
; RV32I-NEXT: mv a1, s2
@@ -460,8 +460,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
460460
; RV32M-NEXT: or a2, a0, a1
461461
; RV32M-NEXT: beqz a2, .LBB3_3
462462
; RV32M-NEXT: # %bb.1: # %cond.false
463-
; RV32M-NEXT: lui a2, 30667
464-
; RV32M-NEXT: addi a3, a2, 1329
463+
; RV32M-NEXT: lui a3, 30667
464+
; RV32M-NEXT: addi a3, a3, 1329
465465
; RV32M-NEXT: lui a2, %hi(.LCPI3_0)
466466
; RV32M-NEXT: addi a2, a2, %lo(.LCPI3_0)
467467
; RV32M-NEXT: bnez a0, .LBB3_4
@@ -847,8 +847,8 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
847847
; RV32I-NEXT: mv s2, a0
848848
; RV32I-NEXT: neg a0, a0
849849
; RV32I-NEXT: and a0, s2, a0
850-
; RV32I-NEXT: lui a1, 30667
851-
; RV32I-NEXT: addi s3, a1, 1329
850+
; RV32I-NEXT: lui s3, 30667
851+
; RV32I-NEXT: addi s3, s3, 1329
852852
; RV32I-NEXT: mv a1, s3
853853
; RV32I-NEXT: call __mulsi3
854854
; RV32I-NEXT: mv s0, a0
@@ -900,8 +900,8 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
900900
;
901901
; RV32M-LABEL: test_cttz_i64_zero_undef:
902902
; RV32M: # %bb.0:
903-
; RV32M-NEXT: lui a2, 30667
904-
; RV32M-NEXT: addi a3, a2, 1329
903+
; RV32M-NEXT: lui a3, 30667
904+
; RV32M-NEXT: addi a3, a3, 1329
905905
; RV32M-NEXT: lui a2, %hi(.LCPI7_0)
906906
; RV32M-NEXT: addi a2, a2, %lo(.LCPI7_0)
907907
; RV32M-NEXT: bnez a0, .LBB7_2

‎llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,8 @@ define signext i32 @ctz_dereferencing_pointer(ptr %b) nounwind {
4343
; RV32I-NEXT: lw s4, 4(a0)
4444
; RV32I-NEXT: neg a0, s2
4545
; RV32I-NEXT: and a0, s2, a0
46-
; RV32I-NEXT: lui a1, 30667
47-
; RV32I-NEXT: addi s1, a1, 1329
46+
; RV32I-NEXT: lui s1, 30667
47+
; RV32I-NEXT: addi s1, s1, 1329
4848
; RV32I-NEXT: mv a1, s1
4949
; RV32I-NEXT: call __mulsi3
5050
; RV32I-NEXT: mv s0, a0
@@ -563,8 +563,8 @@ define signext i32 @ctz4(i64 %b) nounwind {
563563
; RV32I-NEXT: mv s0, a0
564564
; RV32I-NEXT: neg a0, a0
565565
; RV32I-NEXT: and a0, s0, a0
566-
; RV32I-NEXT: lui a1, 30667
567-
; RV32I-NEXT: addi s3, a1, 1329
566+
; RV32I-NEXT: lui s3, 30667
567+
; RV32I-NEXT: addi s3, s3, 1329
568568
; RV32I-NEXT: mv a1, s3
569569
; RV32I-NEXT: call __mulsi3
570570
; RV32I-NEXT: mv s1, a0

‎llvm/test/CodeGen/RISCV/double-convert.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1691,9 +1691,8 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
16911691
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
16921692
; RV32I-NEXT: mv s0, a1
16931693
; RV32I-NEXT: mv s1, a0
1694-
; RV32I-NEXT: lui a0, 265728
1695-
; RV32I-NEXT: addi a3, a0, -64
1696-
; RV32I-NEXT: mv a0, s1
1694+
; RV32I-NEXT: lui a3, 265728
1695+
; RV32I-NEXT: addi a3, a3, -64
16971696
; RV32I-NEXT: li a2, 0
16981697
; RV32I-NEXT: call __gtdf2
16991698
; RV32I-NEXT: mv s2, a0

‎llvm/test/CodeGen/RISCV/float-convert.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1474,8 +1474,8 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
14741474
; RV32I-NEXT: # %bb.1: # %start
14751475
; RV32I-NEXT: lui s1, 1048568
14761476
; RV32I-NEXT: .LBB24_2: # %start
1477-
; RV32I-NEXT: lui a0, 290816
1478-
; RV32I-NEXT: addi a1, a0, -512
1477+
; RV32I-NEXT: lui a1, 290816
1478+
; RV32I-NEXT: addi a1, a1, -512
14791479
; RV32I-NEXT: mv a0, s0
14801480
; RV32I-NEXT: call __gtsf2
14811481
; RV32I-NEXT: blez a0, .LBB24_4
@@ -1516,8 +1516,8 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
15161516
; RV64I-NEXT: # %bb.1: # %start
15171517
; RV64I-NEXT: lui s1, 1048568
15181518
; RV64I-NEXT: .LBB24_2: # %start
1519-
; RV64I-NEXT: lui a0, 290816
1520-
; RV64I-NEXT: addi a1, a0, -512
1519+
; RV64I-NEXT: lui a1, 290816
1520+
; RV64I-NEXT: addi a1, a1, -512
15211521
; RV64I-NEXT: mv a0, s0
15221522
; RV64I-NEXT: call __gtsf2
15231523
; RV64I-NEXT: blez a0, .LBB24_4
@@ -1640,8 +1640,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
16401640
; RV32I-NEXT: mv a0, s2
16411641
; RV32I-NEXT: call __fixunssfsi
16421642
; RV32I-NEXT: mv s1, a0
1643-
; RV32I-NEXT: lui a0, 292864
1644-
; RV32I-NEXT: addi a1, a0, -256
1643+
; RV32I-NEXT: lui a1, 292864
1644+
; RV32I-NEXT: addi a1, a1, -256
16451645
; RV32I-NEXT: mv a0, s2
16461646
; RV32I-NEXT: call __gtsf2
16471647
; RV32I-NEXT: lui a1, 16
@@ -1677,8 +1677,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
16771677
; RV64I-NEXT: mv a0, s2
16781678
; RV64I-NEXT: call __fixunssfdi
16791679
; RV64I-NEXT: mv s1, a0
1680-
; RV64I-NEXT: lui a0, 292864
1681-
; RV64I-NEXT: addi a1, a0, -256
1680+
; RV64I-NEXT: lui a1, 292864
1681+
; RV64I-NEXT: addi a1, a1, -256
16821682
; RV64I-NEXT: mv a0, s2
16831683
; RV64I-NEXT: call __gtsf2
16841684
; RV64I-NEXT: lui a1, 16

‎llvm/test/CodeGen/RISCV/half-convert.ll‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -328,8 +328,8 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
328328
; RV32I-NEXT: # %bb.1: # %start
329329
; RV32I-NEXT: lui s1, 1048568
330330
; RV32I-NEXT: .LBB1_2: # %start
331-
; RV32I-NEXT: lui a0, 290816
332-
; RV32I-NEXT: addi a1, a0, -512
331+
; RV32I-NEXT: lui a1, 290816
332+
; RV32I-NEXT: addi a1, a1, -512
333333
; RV32I-NEXT: mv a0, s0
334334
; RV32I-NEXT: call __gtsf2
335335
; RV32I-NEXT: blez a0, .LBB1_4
@@ -371,8 +371,8 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
371371
; RV64I-NEXT: # %bb.1: # %start
372372
; RV64I-NEXT: lui s1, 1048568
373373
; RV64I-NEXT: .LBB1_2: # %start
374-
; RV64I-NEXT: lui a0, 290816
375-
; RV64I-NEXT: addi a1, a0, -512
374+
; RV64I-NEXT: lui a1, 290816
375+
; RV64I-NEXT: addi a1, a1, -512
376376
; RV64I-NEXT: mv a0, s0
377377
; RV64I-NEXT: call __gtsf2
378378
; RV64I-NEXT: blez a0, .LBB1_4
@@ -812,8 +812,8 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
812812
; RV32I-NEXT: li a1, 0
813813
; RV32I-NEXT: call __gesf2
814814
; RV32I-NEXT: mv s2, a0
815-
; RV32I-NEXT: lui a0, 292864
816-
; RV32I-NEXT: addi a1, a0, -256
815+
; RV32I-NEXT: lui a1, 292864
816+
; RV32I-NEXT: addi a1, a1, -256
817817
; RV32I-NEXT: mv a0, s3
818818
; RV32I-NEXT: call __gtsf2
819819
; RV32I-NEXT: bgtz a0, .LBB3_2
@@ -850,8 +850,8 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
850850
; RV64I-NEXT: li a1, 0
851851
; RV64I-NEXT: call __gesf2
852852
; RV64I-NEXT: mv s2, a0
853-
; RV64I-NEXT: lui a0, 292864
854-
; RV64I-NEXT: addi a1, a0, -256
853+
; RV64I-NEXT: lui a1, 292864
854+
; RV64I-NEXT: addi a1, a1, -256
855855
; RV64I-NEXT: mv a0, s3
856856
; RV64I-NEXT: call __gtsf2
857857
; RV64I-NEXT: bgtz a0, .LBB3_2
@@ -6416,8 +6416,8 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
64166416
; RV32I-NEXT: # %bb.1: # %start
64176417
; RV32I-NEXT: lui s1, 1048568
64186418
; RV32I-NEXT: .LBB32_2: # %start
6419-
; RV32I-NEXT: lui a0, 290816
6420-
; RV32I-NEXT: addi a1, a0, -512
6419+
; RV32I-NEXT: lui a1, 290816
6420+
; RV32I-NEXT: addi a1, a1, -512
64216421
; RV32I-NEXT: mv a0, s0
64226422
; RV32I-NEXT: call __gtsf2
64236423
; RV32I-NEXT: blez a0, .LBB32_4
@@ -6461,8 +6461,8 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
64616461
; RV64I-NEXT: # %bb.1: # %start
64626462
; RV64I-NEXT: lui s1, 1048568
64636463
; RV64I-NEXT: .LBB32_2: # %start
6464-
; RV64I-NEXT: lui a0, 290816
6465-
; RV64I-NEXT: addi a1, a0, -512
6464+
; RV64I-NEXT: lui a1, 290816
6465+
; RV64I-NEXT: addi a1, a1, -512
64666466
; RV64I-NEXT: mv a0, s0
64676467
; RV64I-NEXT: call __gtsf2
64686468
; RV64I-NEXT: blez a0, .LBB32_4
@@ -6903,8 +6903,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
69036903
; RV32I-NEXT: li a1, 0
69046904
; RV32I-NEXT: call __gesf2
69056905
; RV32I-NEXT: mv s1, a0
6906-
; RV32I-NEXT: lui a0, 292864
6907-
; RV32I-NEXT: addi a1, a0, -256
6906+
; RV32I-NEXT: lui a1, 292864
6907+
; RV32I-NEXT: addi a1, a1, -256
69086908
; RV32I-NEXT: mv a0, s2
69096909
; RV32I-NEXT: call __gtsf2
69106910
; RV32I-NEXT: blez a0, .LBB34_2
@@ -6944,8 +6944,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
69446944
; RV64I-NEXT: li a1, 0
69456945
; RV64I-NEXT: call __gesf2
69466946
; RV64I-NEXT: mv s1, a0
6947-
; RV64I-NEXT: lui a0, 292864
6948-
; RV64I-NEXT: addi a1, a0, -256
6947+
; RV64I-NEXT: lui a1, 292864
6948+
; RV64I-NEXT: addi a1, a1, -256
69496949
; RV64I-NEXT: mv a0, s2
69506950
; RV64I-NEXT: call __gtsf2
69516951
; RV64I-NEXT: blez a0, .LBB34_2

‎llvm/test/CodeGen/RISCV/imm.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -837,8 +837,8 @@ define i64 @imm64_5() nounwind {
837837
define i64 @imm64_6() nounwind {
838838
; RV32I-LABEL: imm64_6:
839839
; RV32I: # %bb.0:
840-
; RV32I-NEXT: lui a0, 74565
841-
; RV32I-NEXT: addi a1, a0, 1656
840+
; RV32I-NEXT: lui a1, 74565
841+
; RV32I-NEXT: addi a1, a1, 1656
842842
; RV32I-NEXT: li a0, 0
843843
; RV32I-NEXT: ret
844844
;
@@ -3895,8 +3895,8 @@ define i64 @imm_neg_10307948543() {
38953895
define i64 @li_rori_1() {
38963896
; RV32I-LABEL: li_rori_1:
38973897
; RV32I: # %bb.0:
3898-
; RV32I-NEXT: lui a0, 1048567
3899-
; RV32I-NEXT: addi a1, a0, 2047
3898+
; RV32I-NEXT: lui a1, 1048567
3899+
; RV32I-NEXT: addi a1, a1, 2047
39003900
; RV32I-NEXT: li a0, -1
39013901
; RV32I-NEXT: ret
39023902
;

0 commit comments

Comments
 (0)