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First patch for failing tests
1 parent a8569f2 commit 59a800d

12 files changed

+189
-175
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -785,7 +785,8 @@ bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR(MachineInstr &MI) const {
785785
// TODO: This should probably be a combine somewhere
786786
// (build_vector $src0, undef) -> copy $src0
787787
MachineInstr *Src1Def = getDefIgnoringCopies(Src1, *MRI);
788-
if (Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF) {
788+
if (Src1Def->getOpcode() == AMDGPU::G_IMPLICIT_DEF ||
789+
Src1Def->getOpcode() == AMDGPU::G_POISON) {
789790
MI.setDesc(TII.get(AMDGPU::COPY));
790791
MI.removeOperand(2);
791792
const auto &RC =
@@ -4955,6 +4956,7 @@ AMDGPUInstructionSelector::selectGlobalSAddr(MachineOperand &Root) const {
49554956
// FIXME: We should probably have folded COPY (G_IMPLICIT_DEF) earlier, and
49564957
// drop this.
49574958
if (AddrDef->MI->getOpcode() == AMDGPU::G_IMPLICIT_DEF ||
4959+
AddrDef->MI->getOpcode() == AMDGPU::G_POISON ||
49584960
AddrDef->MI->getOpcode() == AMDGPU::G_CONSTANT || !isSGPR(AddrDef->Reg))
49594961
return std::nullopt;
49604962

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -901,7 +901,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
901901
.legalFor({S32, S64, S16})
902902
.clampScalar(0, S16, S64);
903903

904-
getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE})
904+
getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_POISON, G_FREEZE})
905905
.legalIf(isRegisterClassType(ST, 0))
906906
// s1 and s16 are special cases because they have legal operations on
907907
// them, but don't really occupy registers in the normal way.

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -316,7 +316,7 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
316316
}
317317

318318
if ((Opc == AMDGPU::G_CONSTANT || Opc == AMDGPU::G_FCONSTANT ||
319-
Opc == AMDGPU::G_IMPLICIT_DEF)) {
319+
Opc == AMDGPU::G_IMPLICIT_DEF || Opc == AMDGPU::G_POISON)) {
320320
Register Dst = MI->getOperand(0).getReg();
321321
// Non S1 types are trivially accepted.
322322
if (MRI.getType(Dst) != LLT::scalar(1)) {

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -450,9 +450,11 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
450450
.Uni(S64, {{Sgpr64}, {Sgpr64, Sgpr32}})
451451
.Div(S64, {{Vgpr64}, {Vgpr64, Vgpr32}});
452452

453-
// Note: we only write S1 rules for G_IMPLICIT_DEF, G_CONSTANT, G_FCONSTANT
453+
// Note: we only write S1 rules for G_IMPLICIT_DEF, G_POISON,
454+
// G_CONSTANT, G_FCONSTANT
454455
// and G_FREEZE here, rest is trivially regbankselected earlier
455-
addRulesForGOpcs({G_IMPLICIT_DEF}).Any({{UniS1}, {{Sgpr32Trunc}, {}}});
456+
addRulesForGOpcs({G_IMPLICIT_DEF, G_POISON})
457+
.Any({{UniS1}, {{Sgpr32Trunc}, {}}});
456458
addRulesForGOpcs({G_CONSTANT})
457459
.Any({{UniS1, _}, {{Sgpr32Trunc}, {None}, UniCstExt}});
458460
addRulesForGOpcs({G_FREEZE}).Any({{DivS1}, {{Vcc}, {Vcc}}});

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2211,7 +2211,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
22112211
MachineRegisterInfo &MRI = OpdMapper.getMRI();
22122212
switch (Opc) {
22132213
case AMDGPU::G_CONSTANT:
2214-
case AMDGPU::G_IMPLICIT_DEF: {
2214+
case AMDGPU::G_IMPLICIT_DEF:
2215+
case AMDGPU::G_POISON: {
22152216
Register DstReg = MI.getOperand(0).getReg();
22162217
LLT DstTy = MRI.getType(DstReg);
22172218
if (DstTy != LLT::scalar(1))
@@ -2231,7 +2232,7 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
22312232
LLVMContext &Ctx = B.getMF().getFunction().getContext();
22322233

22332234
MI.getOperand(0).setReg(NewDstReg);
2234-
if (Opc != AMDGPU::G_IMPLICIT_DEF) {
2235+
if (Opc != AMDGPU::G_IMPLICIT_DEF && Opc != AMDGPU::G_POISON) {
22352236
uint64_t ConstVal = MI.getOperand(1).getCImm()->getZExtValue();
22362237
MI.getOperand(1).setCImm(
22372238
ConstantInt::get(IntegerType::getInt32Ty(Ctx), ConstVal));
@@ -4124,7 +4125,8 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
41244125
OpdsMapping[4] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 64);
41254126
break;
41264127
}
4127-
case AMDGPU::G_IMPLICIT_DEF: {
4128+
case AMDGPU::G_IMPLICIT_DEF:
4129+
case AMDGPU::G_POISON: {
41284130
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
41294131
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
41304132
break;

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-gep.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ define void @ossfuzz65052() {
5959
; O0: bb.1 (%ir-block.0):
6060
; O0-NEXT: successors: %bb.2(0x80000000)
6161
; O0-NEXT: {{ $}}
62-
; O0-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
62+
; O0-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_POISON
6363
; O0-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -170141183460469231731687303715884105728
6464
; O0-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128)
6565
; O0-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
@@ -77,7 +77,7 @@ define void @ossfuzz65052() {
7777
; O3: bb.1 (%ir-block.0):
7878
; O3-NEXT: successors: %bb.2(0x80000000)
7979
; O3-NEXT: {{ $}}
80-
; O3-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
80+
; O3-NEXT: [[DEF:%[0-9]+]]:_(p0) = G_POISON
8181
; O3-NEXT: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 -170141183460469231731687303715884105728
8282
; O3-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128)
8383
; O3-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,10 @@
8282
# DEBUG-NEXT: .. the first uncovered type index: {{[0-9]+}}, OK
8383
# DEBUG-NEXT: .. the first uncovered imm index: {{[0-9]+}}, OK
8484
#
85+
# DEBUG-NEXT: G_POISON (opcode {{[0-9]+}}): 1 type index, 0 imm indices
86+
# DEBUG-NEXT: .. the first uncovered type index: {{[0-9]+}}, OK
87+
# DEBUG-NEXT: .. the first uncovered imm index: {{[0-9]+}}, OK
88+
#
8589
# DEBUG-NEXT: G_PHI (opcode {{[0-9]+}}): 1 type index, 0 imm indices
8690
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
8791
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK

‎llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ define <2 x i12> @ret_v2i12(i12 %v1, i12 %v2) {
4141
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
4242
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
4343
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
44-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s12>) = G_IMPLICIT_DEF
44+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s12>) = G_POISON
4545
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
4646
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
4747
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s12>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s12), [[C]](s64)
@@ -63,7 +63,7 @@ define <3 x i12> @ret_v3i12(i12 %v1, i12 %v2) {
6363
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
6464
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
6565
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
66-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s12>) = G_IMPLICIT_DEF
66+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s12>) = G_POISON
6767
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
6868
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
6969
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -93,7 +93,7 @@ define <4 x i12> @ret_v4i12(i12 %v1, i12 %v2) {
9393
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
9494
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
9595
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
96-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s12>) = G_IMPLICIT_DEF
96+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s12>) = G_POISON
9797
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
9898
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
9999
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -121,7 +121,7 @@ define <5 x i12> @ret_v5i12(i12 %v1, i12 %v2) {
121121
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
122122
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
123123
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
124-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<5 x s12>) = G_IMPLICIT_DEF
124+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<5 x s12>) = G_POISON
125125
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
126126
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
127127
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -161,7 +161,7 @@ define <6 x i12> @ret_v6i12(i12 %v1, i12 %v2) {
161161
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
162162
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
163163
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
164-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<6 x s12>) = G_IMPLICIT_DEF
164+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<6 x s12>) = G_POISON
165165
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
166166
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
167167
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -206,7 +206,7 @@ define <7 x i12> @ret_v7i12(i12 %v1, i12 %v2) {
206206
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
207207
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
208208
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
209-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<7 x s12>) = G_IMPLICIT_DEF
209+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<7 x s12>) = G_POISON
210210
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
211211
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
212212
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -256,7 +256,7 @@ define <8 x i12> @ret_v8i12(i12 %v1, i12 %v2) {
256256
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY]](s32)
257257
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
258258
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
259-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s12>) = G_IMPLICIT_DEF
259+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s12>) = G_POISON
260260
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
261261
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
262262
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -297,7 +297,7 @@ define <12 x i12> @ret_v12i12(i12 %v1, i12 %v2) {
297297
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s12) = G_TRUNC [[COPY1]](s32)
298298
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w1
299299
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s12) = G_TRUNC [[COPY2]](s32)
300-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<12 x s12>) = G_IMPLICIT_DEF
300+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<12 x s12>) = G_POISON
301301
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
302302
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
303303
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -375,7 +375,7 @@ define <2 x i100> @ret_v2i100(i100 %v1, i100 %v2) {
375375
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
376376
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
377377
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
378-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s100>) = G_IMPLICIT_DEF
378+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s100>) = G_POISON
379379
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
380380
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
381381
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s100>) = G_INSERT_VECTOR_ELT [[DEF]], [[TRUNC]](s100), [[C]](s64)
@@ -405,7 +405,7 @@ define <3 x i100> @ret_v3i100(i100 %v1, i100 %v2) {
405405
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
406406
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
407407
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
408-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s100>) = G_IMPLICIT_DEF
408+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<3 x s100>) = G_POISON
409409
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
410410
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
411411
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
@@ -440,7 +440,7 @@ define <4 x i100> @ret_v4i100(i100 %v1, i100 %v2) {
440440
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
441441
; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
442442
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s100) = G_TRUNC [[MV1]](s128)
443-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s100>) = G_IMPLICIT_DEF
443+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s100>) = G_POISON
444444
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
445445
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
446446
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2

‎llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-ilp32-ilp32f-ilp32d-common.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1383,9 +1383,9 @@ define %struct.large2 @callee_large_struct_ret2() nounwind {
13831383
; RV32I-NEXT: liveins: $x10
13841384
; RV32I-NEXT: {{ $}}
13851385
; RV32I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
1386-
; RV32I-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
1386+
; RV32I-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_POISON
13871387
; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
1388-
; RV32I-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
1388+
; RV32I-NEXT: [[DEF1:%[0-9]+]]:_(s16) = G_POISON
13891389
; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
13901390
; RV32I-NEXT: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 2.000000e+00
13911391
; RV32I-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 3

‎llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/calling-conv-lp64-lp64f-lp64d-common.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1156,8 +1156,8 @@ define %struct.large2 @callee_large_struct_ret2() nounwind {
11561156
; RV64I-NEXT: liveins: $x10
11571157
; RV64I-NEXT: {{ $}}
11581158
; RV64I-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
1159-
; RV64I-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
1160-
; RV64I-NEXT: [[DEF1:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
1159+
; RV64I-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_POISON
1160+
; RV64I-NEXT: [[DEF1:%[0-9]+]]:_(s128) = G_POISON
11611161
; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
11621162
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
11631163
; RV64I-NEXT: [[C1:%[0-9]+]]:_(s128) = G_CONSTANT i128 2

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