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[NFC][AMDGPU] Replace more direct arch comparison with isAMDGCN()
This is an extension of #131357. Hopefully this would be the last one.
1 parent 7598cea commit 59bc234

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10 files changed

+20
-26
lines changed

10 files changed

+20
-26
lines changed

‎clang/include/clang/Driver/ToolChain.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -821,7 +821,7 @@ class ToolChain {
821821
return llvm::Triple("nvptx-nvidia-cuda");
822822
if (TT.getArch() == llvm::Triple::nvptx64)
823823
return llvm::Triple("nvptx64-nvidia-cuda");
824-
if (TT.getArch() == llvm::Triple::amdgcn)
824+
if (TT.isAMDGCN())
825825
return llvm::Triple("amdgcn-amd-amdhsa");
826826
}
827827
return TT;

‎clang/lib/Basic/Targets/AMDGPU.h‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
5252
std::string TargetID;
5353

5454
bool hasFP64() const {
55-
return getTriple().getArch() == llvm::Triple::amdgcn ||
55+
return getTriple().isAMDGCN() ||
5656
!!(GPUFeatures & llvm::AMDGPU::FEATURE_FP64);
5757
}
5858

@@ -63,11 +63,11 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
6363

6464
/// Has fast fma f64
6565
bool hasFastFMA() const {
66-
return getTriple().getArch() == llvm::Triple::amdgcn;
66+
return getTriple().isAMDGCN();
6767
}
6868

6969
bool hasFMAF() const {
70-
return getTriple().getArch() == llvm::Triple::amdgcn ||
70+
return getTriple().isAMDGCN() ||
7171
!!(GPUFeatures & llvm::AMDGPU::FEATURE_FMA);
7272
}
7373

@@ -76,13 +76,11 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
7676
}
7777

7878
bool hasLDEXPF() const {
79-
return getTriple().getArch() == llvm::Triple::amdgcn ||
79+
return getTriple().isAMDGCN() ||
8080
!!(GPUFeatures & llvm::AMDGPU::FEATURE_LDEXP);
8181
}
8282

83-
static bool isAMDGCN(const llvm::Triple &TT) {
84-
return TT.getArch() == llvm::Triple::amdgcn;
85-
}
83+
static bool isAMDGCN(const llvm::Triple &TT) { return TT.isAMDGCN(); }
8684

8785
static bool isR600(const llvm::Triple &TT) {
8886
return TT.getArch() == llvm::Triple::r600;
@@ -125,7 +123,7 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
125123
}
126124

127125
uint64_t getMaxPointerWidth() const override {
128-
return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32;
126+
return getTriple().isAMDGCN() ? 64 : 32;
129127
}
130128

131129
bool hasBFloat16Type() const override { return isAMDGCN(getTriple()); }
@@ -269,15 +267,15 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final : public TargetInfo {
269267
}
270268

271269
bool isValidCPUName(StringRef Name) const override {
272-
if (getTriple().getArch() == llvm::Triple::amdgcn)
270+
if (getTriple().isAMDGCN())
273271
return llvm::AMDGPU::parseArchAMDGCN(Name) != llvm::AMDGPU::GK_NONE;
274272
return llvm::AMDGPU::parseArchR600(Name) != llvm::AMDGPU::GK_NONE;
275273
}
276274

277275
void fillValidCPUList(SmallVectorImpl<StringRef> &Values) const override;
278276

279277
bool setCPU(const std::string &Name) override {
280-
if (getTriple().getArch() == llvm::Triple::amdgcn) {
278+
if (getTriple().isAMDGCN()) {
281279
GPUKind = llvm::AMDGPU::parseArchAMDGCN(Name);
282280
GPUFeatures = llvm::AMDGPU::getArchAttrAMDGCN(GPUKind);
283281
} else {

‎clang/lib/Driver/Driver.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -158,8 +158,7 @@ getHIPOffloadTargetTriple(const Driver &D, const ArgList &Args) {
158158
auto TT = getOffloadTargetTriple(D, Args);
159159
if (!TT)
160160
return std::nullopt;
161-
if (TT->getArch() == llvm::Triple::amdgcn &&
162-
TT->getVendor() == llvm::Triple::AMD &&
161+
if (TT->isAMDGCN() && TT->getVendor() == llvm::Triple::AMD &&
163162
TT->getOS() == llvm::Triple::AMDHSA)
164163
return TT;
165164
if (TT->getArch() == llvm::Triple::spirv64)
@@ -3410,7 +3409,7 @@ class OffloadingActionBuilder final {
34103409
const ToolChain *HostTC = C.getSingleOffloadToolChain<Action::OFK_Host>();
34113410
assert(HostTC && "No toolchain for host compilation.");
34123411
if (HostTC->getTriple().isNVPTX() ||
3413-
HostTC->getTriple().getArch() == llvm::Triple::amdgcn) {
3412+
HostTC->getTriple().isAMDGCN()) {
34143413
// We do not support targeting NVPTX/AMDGCN for host compilation. Throw
34153414
// an error and abort pipeline construction early so we don't trip
34163415
// asserts that assume device-side compilation.

‎clang/lib/Driver/ToolChains/HIPAMD.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -296,7 +296,7 @@ HIPAMDToolChain::TranslateArgs(const llvm::opt::DerivedArgList &Args,
296296
}
297297

298298
Tool *HIPAMDToolChain::buildLinker() const {
299-
assert(getTriple().getArch() == llvm::Triple::amdgcn ||
299+
assert(getTriple().isAMDGCN() ||
300300
getTriple().getArch() == llvm::Triple::spirv64);
301301
return new tools::AMDGCN::Linker(*this);
302302
}

‎clang/lib/Frontend/CompilerInvocation.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4323,7 +4323,7 @@ bool CompilerInvocation::ParseLangArgs(LangOptions &Opts, ArgList &Args,
43234323
TT.getArch() == llvm::Triple::loongarch64 ||
43244324
TT.getArch() == llvm::Triple::nvptx ||
43254325
TT.getArch() == llvm::Triple::nvptx64 ||
4326-
TT.getArch() == llvm::Triple::amdgcn ||
4326+
TT.isAMDGCN() ||
43274327
TT.getArch() == llvm::Triple::x86 ||
43284328
TT.getArch() == llvm::Triple::x86_64))
43294329
Diags.Report(diag::err_drv_invalid_omp_target) << A->getValue(i);

‎flang/lib/Frontend/CompilerInvocation.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1175,7 +1175,7 @@ static bool parseOpenMPArgs(CompilerInvocation &res, llvm::opt::ArgList &args,
11751175
tt.getArch() == llvm::Triple::systemz ||
11761176
tt.getArch() == llvm::Triple::nvptx ||
11771177
tt.getArch() == llvm::Triple::nvptx64 ||
1178-
tt.getArch() == llvm::Triple::amdgcn ||
1178+
tt.isAMDGCN() ||
11791179
tt.getArch() == llvm::Triple::x86 ||
11801180
tt.getArch() == llvm::Triple::x86_64))
11811181
diags.Report(clang::diag::err_drv_invalid_omp_target)

‎llvm/include/llvm/TargetParser/Triple.h‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -888,9 +888,7 @@ class Triple {
888888
/// Tests whether the target is AMDGCN
889889
bool isAMDGCN() const { return getArch() == Triple::amdgcn; }
890890

891-
bool isAMDGPU() const {
892-
return getArch() == Triple::r600 || getArch() == Triple::amdgcn;
893-
}
891+
bool isAMDGPU() const { return getArch() == Triple::r600 || isAMDGCN(); }
894892

895893
/// Tests whether the target is Thumb (little and big endian).
896894
bool isThumb() const {

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -454,8 +454,7 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
454454
// 1 = Vector Register Class
455455
SmallVector<SDValue, 32 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
456456

457-
bool IsGCN = CurDAG->getSubtarget().getTargetTriple().getArch() ==
458-
Triple::amdgcn;
457+
bool IsGCN = CurDAG->getSubtarget().getTargetTriple().isAMDGCN();
459458
RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32);
460459
bool IsRegSeq = true;
461460
unsigned NOps = N->getNumOperands();

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5463,7 +5463,7 @@ bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
54635463
}
54645464

54655465
bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
5466-
if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
5466+
if (!getSTI().getTargetTriple().isAMDGCN())
54675467
return TokError("directive only supported for amdgcn architecture");
54685468

54695469
std::string TargetIDDirective;
@@ -5550,7 +5550,7 @@ bool AMDGPUAsmParser::calculateGPRBlocks(
55505550
}
55515551

55525552
bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
5553-
if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
5553+
if (!getSTI().getTargetTriple().isAMDGCN())
55545554
return TokError("directive only supported for amdgcn architecture");
55555555

55565556
if (!isHsaAbi(getSTI()))
@@ -6142,7 +6142,7 @@ bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
61426142
}
61436143

61446144
bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
6145-
if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
6145+
if (!getSTI().getTargetTriple().isAMDGCN()) {
61466146
return Error(getLoc(),
61476147
".amd_amdgpu_isa directive is not available on non-amdgcn "
61486148
"architectures");

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1004,7 +1004,7 @@ unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
10041004
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI,
10051005
unsigned FlatWorkGroupSize) {
10061006
assert(FlatWorkGroupSize != 0);
1007-
if (STI->getTargetTriple().getArch() != Triple::amdgcn)
1007+
if (!STI->getTargetTriple().isAMDGCN())
10081008
return 8;
10091009
unsigned MaxWaves = getMaxWavesPerEU(STI) * getEUsPerCU(STI);
10101010
unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);

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