Address comments

Author: NickGuy-Arm

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -1831,13 +1831,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   }
 
   // Handle partial reduction operations
-  if (EnablePartialReduceNodes) {
-    if (Subtarget->isSVEorStreamingSVEAvailable()) {
-      // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
-      // Other pairs will default to 'Expand'.
-      setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
-      setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
-    }
+  if (EnablePartialReduceNodes && Subtarget->isSVEorStreamingSVEAvailable()) {
+    // Mark known legal pairs as 'Legal' (these will expand to UDOT or SDOT).
+    // Other pairs will default to 'Expand'.
+    setPartialReduceMLAAction(MVT::nxv2i64, MVT::nxv8i16, Legal);
+    setPartialReduceMLAAction(MVT::nxv4i32, MVT::nxv16i8, Legal);
   }
 
   // Handle operations that are only available in non-streaming SVE mode.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -143,9 +143,6 @@ def HasFuseAES       : Predicate<"Subtarget->hasFuseAES()">,
                                  "fuse-aes">;
 def HasSVE           : Predicate<"Subtarget->isSVEAvailable()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSVE), "sve">;
-def HasSVEorStreamingSVE 
-                     : Predicate<"Subtarget->isSVEorStreamingSVEAvailable()">, 
-                                 AssemblerPredicateWithAll<(all_of FeatureSVE), "sve">;
 def HasSVEB16B16     : Predicate<"Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSVEB16B16()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSVEB16B16), "sve-b16b16">;
 def HasSVE2          : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE2()">,

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

@@ -655,7 +655,7 @@ let Predicates = [HasSVE_or_SME] in {
   defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot", AArch64sdot>;
   defm UDOT_ZZZ : sve_intx_dot<0b1, "udot", AArch64udot>;
 
-  let Predicates = [HasSVEorStreamingSVE] in {
+  let Predicates = [HasSVE_or_SME] in {
     def : Pat<(nxv4i32 (partial_reduce_umla nxv4i32:$Acc, nxv16i8:$MulLHS, nxv16i8:$MulRHS)),
               (UDOT_ZZZ_S $Acc, $MulLHS, $MulRHS)>;
     def : Pat<(nxv4i32 (partial_reduce_smla nxv4i32:$Acc, nxv16i8:$MulLHS, nxv16i8:$MulRHS)),
@@ -664,7 +664,7 @@ let Predicates = [HasSVE_or_SME] in {
               (UDOT_ZZZ_D $Acc, $MulLHS, $MulRHS)>;
     def : Pat<(nxv2i64 (partial_reduce_smla nxv2i64:$Acc, nxv8i16:$MulLHS, nxv8i16:$MulRHS)),
               (SDOT_ZZZ_D $Acc, $MulLHS, $MulRHS)>;
-  } // End HasSVEorStreamingSVE
+  } // End HasSVE_or_SME
 
   defm SDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b0, "sdot", int_aarch64_sve_sdot_lane>;
   defm UDOT_ZZZI : sve_intx_dot_by_indexed_elem<0b1, "udot", int_aarch64_sve_udot_lane>;