[LV] Add test with to check different interleave counts for fmaxnum.

fhahn · fhahn · commit 59d2e9359089 · 2025-11-15T15:51:28.000Z
This adds additional test coverage for folding FCMP uno (#166823)
diff --git a/llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll b/llvm/test/Transforms/LoopVectorize/fcmp-uno-fold-interleave.ll
@@ -0,0 +1,211 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "loop:" --version 6
+; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=3 -S %s | FileCheck --check-prefix=IC3 %s
+; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=4 -S %s | FileCheck --check-prefix=IC4 %s
+; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=5 -S %s | FileCheck --check-prefix=IC5 %s
+
+define float @fmaxnum(ptr %src, i64 %n) {
+; IC3-LABEL: define float @fmaxnum(
+; IC3-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
+; IC3-NEXT:  [[ENTRY:.*]]:
+; IC3-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 12
+; IC3-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; IC3:       [[VECTOR_PH]]:
+; IC3-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 12
+; IC3-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; IC3-NEXT:    br label %[[VECTOR_BODY:.*]]
+; IC3:       [[VECTOR_BODY]]:
+; IC3-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT:    [[VEC_PHI2:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; IC3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[INDEX]]
+; IC3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 4
+; IC3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 8
+; IC3-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4
+; IC3-NEXT:    [[WIDE_LOAD3:%.*]] = load <4 x float>, ptr [[TMP1]], align 4
+; IC3-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
+; IC3-NEXT:    [[TMP3]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]])
+; IC3-NEXT:    [[TMP4]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI1]], <4 x float> [[WIDE_LOAD3]])
+; IC3-NEXT:    [[TMP5]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI2]], <4 x float> [[WIDE_LOAD4]])
+; IC3-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 12
+; IC3-NEXT:    [[TMP6:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]
+; IC3-NEXT:    [[TMP7:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD3]], [[WIDE_LOAD3]]
+; IC3-NEXT:    [[TMP8:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD4]], [[WIDE_LOAD4]]
+; IC3-NEXT:    [[TMP9:%.*]] = freeze <4 x i1> [[TMP6]]
+; IC3-NEXT:    [[TMP10:%.*]] = freeze <4 x i1> [[TMP7]]
+; IC3-NEXT:    [[TMP11:%.*]] = or <4 x i1> [[TMP9]], [[TMP10]]
+; IC3-NEXT:    [[TMP12:%.*]] = freeze <4 x i1> [[TMP8]]
+; IC3-NEXT:    [[TMP13:%.*]] = or <4 x i1> [[TMP11]], [[TMP12]]
+; IC3-NEXT:    [[TMP14:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP13]])
+; IC3-NEXT:    [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; IC3-NEXT:    [[TMP16:%.*]] = or i1 [[TMP14]], [[TMP15]]
+; IC3-NEXT:    br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; IC3:       [[MIDDLE_BLOCK]]:
+; IC3-NEXT:    [[TMP17:%.*]] = select i1 [[TMP14]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP3]]
+; IC3-NEXT:    [[TMP18:%.*]] = select i1 [[TMP14]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP4]]
+; IC3-NEXT:    [[TMP19:%.*]] = select i1 [[TMP14]], <4 x float> [[VEC_PHI2]], <4 x float> [[TMP5]]
+; IC3-NEXT:    [[TMP20:%.*]] = select i1 [[TMP14]], i64 [[INDEX]], i64 [[N_VEC]]
+; IC3-NEXT:    [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP17]], <4 x float> [[TMP18]])
+; IC3-NEXT:    [[RDX_MINMAX5:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_MINMAX]], <4 x float> [[TMP19]])
+; IC3-NEXT:    [[TMP21:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[RDX_MINMAX5]])
+; IC3-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; IC3-NEXT:    [[TMP22:%.*]] = xor i1 [[TMP14]], true
+; IC3-NEXT:    [[TMP23:%.*]] = and i1 [[CMP_N]], [[TMP22]]
+; IC3-NEXT:    br i1 [[TMP23]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
+; IC3:       [[SCALAR_PH]]:
+; IC3-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC3-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ -1.000000e+07, %[[ENTRY]] ]
+; IC3-NEXT:    br label %[[LOOP:.*]]
+; IC3:       [[LOOP]]:
+;
+; IC4-LABEL: define float @fmaxnum(
+; IC4-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
+; IC4-NEXT:  [[ENTRY:.*]]:
+; IC4-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16
+; IC4-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; IC4:       [[VECTOR_PH]]:
+; IC4-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 16
+; IC4-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; IC4-NEXT:    br label %[[VECTOR_BODY:.*]]
+; IC4:       [[VECTOR_BODY]]:
+; IC4-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT:    [[VEC_PHI2:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT:    [[VEC_PHI3:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; IC4-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[INDEX]]
+; IC4-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 4
+; IC4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 8
+; IC4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 12
+; IC4-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4
+; IC4-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP1]], align 4
+; IC4-NEXT:    [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
+; IC4-NEXT:    [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP3]], align 4
+; IC4-NEXT:    [[TMP4]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]])
+; IC4-NEXT:    [[TMP5]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI1]], <4 x float> [[WIDE_LOAD4]])
+; IC4-NEXT:    [[TMP6]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI2]], <4 x float> [[WIDE_LOAD5]])
+; IC4-NEXT:    [[TMP7]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI3]], <4 x float> [[WIDE_LOAD6]])
+; IC4-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
+; IC4-NEXT:    [[TMP8:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]
+; IC4-NEXT:    [[TMP9:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD4]], [[WIDE_LOAD4]]
+; IC4-NEXT:    [[TMP24:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD5]], [[WIDE_LOAD5]]
+; IC4-NEXT:    [[TMP25:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD6]], [[WIDE_LOAD6]]
+; IC4-NEXT:    [[TMP10:%.*]] = freeze <4 x i1> [[TMP8]]
+; IC4-NEXT:    [[TMP11:%.*]] = freeze <4 x i1> [[TMP9]]
+; IC4-NEXT:    [[TMP12:%.*]] = or <4 x i1> [[TMP10]], [[TMP11]]
+; IC4-NEXT:    [[TMP26:%.*]] = freeze <4 x i1> [[TMP24]]
+; IC4-NEXT:    [[TMP27:%.*]] = or <4 x i1> [[TMP12]], [[TMP26]]
+; IC4-NEXT:    [[TMP28:%.*]] = freeze <4 x i1> [[TMP25]]
+; IC4-NEXT:    [[TMP29:%.*]] = or <4 x i1> [[TMP27]], [[TMP28]]
+; IC4-NEXT:    [[TMP13:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP29]])
+; IC4-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; IC4-NEXT:    [[TMP15:%.*]] = or i1 [[TMP13]], [[TMP14]]
+; IC4-NEXT:    br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; IC4:       [[MIDDLE_BLOCK]]:
+; IC4-NEXT:    [[TMP16:%.*]] = select i1 [[TMP13]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP4]]
+; IC4-NEXT:    [[TMP17:%.*]] = select i1 [[TMP13]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP5]]
+; IC4-NEXT:    [[TMP18:%.*]] = select i1 [[TMP13]], <4 x float> [[VEC_PHI2]], <4 x float> [[TMP6]]
+; IC4-NEXT:    [[TMP19:%.*]] = select i1 [[TMP13]], <4 x float> [[VEC_PHI3]], <4 x float> [[TMP7]]
+; IC4-NEXT:    [[TMP20:%.*]] = select i1 [[TMP13]], i64 [[INDEX]], i64 [[N_VEC]]
+; IC4-NEXT:    [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP16]], <4 x float> [[TMP17]])
+; IC4-NEXT:    [[RDX_MINMAX7:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_MINMAX]], <4 x float> [[TMP18]])
+; IC4-NEXT:    [[RDX_MINMAX8:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_MINMAX7]], <4 x float> [[TMP19]])
+; IC4-NEXT:    [[TMP21:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[RDX_MINMAX8]])
+; IC4-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; IC4-NEXT:    [[TMP22:%.*]] = xor i1 [[TMP13]], true
+; IC4-NEXT:    [[TMP23:%.*]] = and i1 [[CMP_N]], [[TMP22]]
+; IC4-NEXT:    br i1 [[TMP23]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
+; IC4:       [[SCALAR_PH]]:
+; IC4-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP20]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC4-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP21]], %[[MIDDLE_BLOCK]] ], [ -1.000000e+07, %[[ENTRY]] ]
+; IC4-NEXT:    br label %[[LOOP:.*]]
+; IC4:       [[LOOP]]:
+;
+; IC5-LABEL: define float @fmaxnum(
+; IC5-SAME: ptr [[SRC:%.*]], i64 [[N:%.*]]) {
+; IC5-NEXT:  [[ENTRY:.*]]:
+; IC5-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 20
+; IC5-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; IC5:       [[VECTOR_PH]]:
+; IC5-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 20
+; IC5-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
+; IC5-NEXT:    br label %[[VECTOR_BODY:.*]]
+; IC5:       [[VECTOR_BODY]]:
+; IC5-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; IC5-NEXT:    [[VEC_PHI:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; IC5-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ]
+; IC5-NEXT:    [[VEC_PHI2:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ]
+; IC5-NEXT:    [[VEC_PHI3:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP8:%.*]], %[[VECTOR_BODY]] ]
+; IC5-NEXT:    [[VEC_PHI4:%.*]] = phi <4 x float> [ splat (float -1.000000e+07), %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ]
+; IC5-NEXT:    [[TMP0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC]], i64 [[INDEX]]
+; IC5-NEXT:    [[TMP1:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 4
+; IC5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 8
+; IC5-NEXT:    [[TMP3:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 12
+; IC5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds nuw float, ptr [[TMP0]], i32 16
+; IC5-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP0]], align 4
+; IC5-NEXT:    [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP1]], align 4
+; IC5-NEXT:    [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
+; IC5-NEXT:    [[WIDE_LOAD7:%.*]] = load <4 x float>, ptr [[TMP3]], align 4
+; IC5-NEXT:    [[WIDE_LOAD8:%.*]] = load <4 x float>, ptr [[TMP4]], align 4
+; IC5-NEXT:    [[TMP5]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]])
+; IC5-NEXT:    [[TMP6]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI1]], <4 x float> [[WIDE_LOAD5]])
+; IC5-NEXT:    [[TMP7]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI2]], <4 x float> [[WIDE_LOAD6]])
+; IC5-NEXT:    [[TMP8]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI3]], <4 x float> [[WIDE_LOAD7]])
+; IC5-NEXT:    [[TMP9]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[VEC_PHI4]], <4 x float> [[WIDE_LOAD8]])
+; IC5-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 20
+; IC5-NEXT:    [[TMP10:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD]]
+; IC5-NEXT:    [[TMP11:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD5]], [[WIDE_LOAD5]]
+; IC5-NEXT:    [[TMP12:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD6]], [[WIDE_LOAD6]]
+; IC5-NEXT:    [[TMP13:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD7]], [[WIDE_LOAD7]]
+; IC5-NEXT:    [[TMP14:%.*]] = fcmp uno <4 x float> [[WIDE_LOAD8]], [[WIDE_LOAD8]]
+; IC5-NEXT:    [[TMP15:%.*]] = freeze <4 x i1> [[TMP10]]
+; IC5-NEXT:    [[TMP16:%.*]] = freeze <4 x i1> [[TMP11]]
+; IC5-NEXT:    [[TMP17:%.*]] = or <4 x i1> [[TMP15]], [[TMP16]]
+; IC5-NEXT:    [[TMP18:%.*]] = freeze <4 x i1> [[TMP12]]
+; IC5-NEXT:    [[TMP19:%.*]] = or <4 x i1> [[TMP17]], [[TMP18]]
+; IC5-NEXT:    [[TMP20:%.*]] = freeze <4 x i1> [[TMP13]]
+; IC5-NEXT:    [[TMP21:%.*]] = or <4 x i1> [[TMP19]], [[TMP20]]
+; IC5-NEXT:    [[TMP22:%.*]] = freeze <4 x i1> [[TMP14]]
+; IC5-NEXT:    [[TMP23:%.*]] = or <4 x i1> [[TMP21]], [[TMP22]]
+; IC5-NEXT:    [[TMP24:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP23]])
+; IC5-NEXT:    [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; IC5-NEXT:    [[TMP26:%.*]] = or i1 [[TMP24]], [[TMP25]]
+; IC5-NEXT:    br i1 [[TMP26]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; IC5:       [[MIDDLE_BLOCK]]:
+; IC5-NEXT:    [[TMP27:%.*]] = select i1 [[TMP24]], <4 x float> [[VEC_PHI]], <4 x float> [[TMP5]]
+; IC5-NEXT:    [[TMP28:%.*]] = select i1 [[TMP24]], <4 x float> [[VEC_PHI1]], <4 x float> [[TMP6]]
+; IC5-NEXT:    [[TMP29:%.*]] = select i1 [[TMP24]], <4 x float> [[VEC_PHI2]], <4 x float> [[TMP7]]
+; IC5-NEXT:    [[TMP30:%.*]] = select i1 [[TMP24]], <4 x float> [[VEC_PHI3]], <4 x float> [[TMP8]]
+; IC5-NEXT:    [[TMP31:%.*]] = select i1 [[TMP24]], <4 x float> [[VEC_PHI4]], <4 x float> [[TMP9]]
+; IC5-NEXT:    [[TMP32:%.*]] = select i1 [[TMP24]], i64 [[INDEX]], i64 [[N_VEC]]
+; IC5-NEXT:    [[RDX_MINMAX:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP27]], <4 x float> [[TMP28]])
+; IC5-NEXT:    [[RDX_MINMAX9:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_MINMAX]], <4 x float> [[TMP29]])
+; IC5-NEXT:    [[RDX_MINMAX10:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_MINMAX9]], <4 x float> [[TMP30]])
+; IC5-NEXT:    [[RDX_MINMAX11:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[RDX_MINMAX10]], <4 x float> [[TMP31]])
+; IC5-NEXT:    [[TMP33:%.*]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[RDX_MINMAX11]])
+; IC5-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
+; IC5-NEXT:    [[TMP34:%.*]] = xor i1 [[TMP24]], true
+; IC5-NEXT:    [[TMP35:%.*]] = and i1 [[CMP_N]], [[TMP34]]
+; IC5-NEXT:    br i1 [[TMP35]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
+; IC5:       [[SCALAR_PH]]:
+; IC5-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP32]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
+; IC5-NEXT:    [[BC_MERGE_RDX:%.*]] = phi float [ [[TMP33]], %[[MIDDLE_BLOCK]] ], [ -1.000000e+07, %[[ENTRY]] ]
+; IC5-NEXT:    br label %[[LOOP:.*]]
+; IC5:       [[LOOP]]:
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %max = phi float [ -1.000000e+07, %entry ], [ %max.next, %loop ]
+  %gep.src = getelementptr inbounds nuw float, ptr %src, i64 %iv
+  %l = load float, ptr %gep.src, align 4
+  %max.next = call float @llvm.maxnum.f32(float %max, float %l)
+  %iv.next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv.next, %n
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret float %max.next
+}
