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Add is_canonicalized and remove some of the unnecessary changes
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6 files changed

+10
-10
lines changed

6 files changed

+10
-10
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llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1052,9 +1052,9 @@ def AArch64CttzElts : SDNode<"AArch64ISD::CTTZ_ELTS", SDTypeProfile<1, 1,
10521052
// have no common bits.
10531053
def add_and_or_is_add : PatFrags<(ops node:$lhs, node:$rhs),
10541054
[(add node:$lhs, node:$rhs), (or node:$lhs, node:$rhs)],[{
1055-
if (Op.getOpcode() == ISD::ADD)
1055+
if (N->getOpcode() == ISD::ADD)
10561056
return true;
1057-
return CurDAG->isADDLike(Op);
1057+
return CurDAG->isADDLike(SDValue(N,0));
10581058
}]> {
10591059
let GISelPredicateCode = [{
10601060
return mi_match(MI, MRI, m_GAddLike(m_Reg(), m_Reg()));

llvm/lib/Target/AMDGPU/AMDGPUInstructions.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -858,7 +858,7 @@ def fmaxnum_like : PatFrags<(ops node:$src0, node:$src1),
858858

859859
class NeverNaNPats<dag ops, list<dag> frags> : PatFrags<ops, frags> {
860860
let PredicateCode = [{
861-
return CurDAG->isKnownNeverNaN(Op);
861+
return CurDAG->isKnownNeverNaN(SDValue(N,0));
862862
}];
863863
let GISelPredicateCode = [{
864864
return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI);

llvm/lib/Target/AMDGPU/R600Instructions.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -287,12 +287,12 @@ class VTX_READ <string name, dag outs, list<dag> pattern>
287287
def atomic_cmp_swap_global_noret : PatFrag<
288288
(ops node:$ptr, node:$cmp, node:$value),
289289
(atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
290-
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (Op.use_empty());}]>;
290+
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (SDValue(N, 0).use_empty());}]>;
291291

292292
def atomic_cmp_swap_global_ret : PatFrag<
293293
(ops node:$ptr, node:$cmp, node:$value),
294294
(atomic_cmp_swap node:$ptr, node:$cmp, node:$value),
295-
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!Op.use_empty());}]>;
295+
[{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS && (!SDValue(N, 0).use_empty());}]>;
296296

297297
def mskor_global : PatFrag<(ops node:$val, node:$ptr),
298298
(AMDGPUstore_mskor node:$val, node:$ptr), [{

llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -969,7 +969,7 @@ def MFMALdScaleXForm : SDNodeXForm<timm, [{
969969
def is_canonicalized : PatLeaf<(fAny srcvalue:$src), [{
970970
const SITargetLowering &Lowering =
971971
*static_cast<const SITargetLowering *>(getTargetLowering());
972-
return Lowering.isCanonicalized(*CurDAG, SDValue(N, 0));
972+
return Lowering.isCanonicalized(*CurDAG, Op);
973973
}]> {
974974
let GISelPredicateCode = [{
975975
const SITargetLowering *TLI = static_cast<const SITargetLowering *>(

llvm/lib/Target/BPF/BPFInstrInfo.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1023,12 +1023,12 @@ foreach P = [[atomic_load_sub_i64_monotonic, XADDD],
10231023
class binop_no_use<SDPatternOperator operator>
10241024
: PatFrag<(ops node:$A, node:$B),
10251025
(operator node:$A, node:$B),
1026-
[{ return Op.use_empty(); }]>;
1026+
[{ return SDValue(N, 0).use_empty(); }]>;
10271027

10281028
class binop_has_use<SDPatternOperator operator>
10291029
: PatFrag<(ops node:$A, node:$B),
10301030
(operator node:$A, node:$B),
1031-
[{ return !Op.use_empty(); }]>;
1031+
[{ return !SDValue(N, 0).use_empty(); }]>;
10321032

10331033
foreach op = [add, and, or, xor] in {
10341034
def atomic_load_ # op # _i64_monotonic_nu:

llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5705,7 +5705,7 @@ let Predicates = [UseSSE41, OptForSize] in {
57055705
// commuting would change which operand is inverted.
57065706
def X86ptest_commutable : PatFrag<(ops node:$src1, node:$src2),
57075707
(X86ptest node:$src1, node:$src2), [{
5708-
return onlyUsesZeroFlag(Op);
5708+
return onlyUsesZeroFlag(SDValue(N, 0));
57095709
}]>;
57105710

57115711
// ptest instruction we'll lower to this in X86ISelLowering primarily from
@@ -5772,7 +5772,7 @@ multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
57725772
// used, commuting would change which operand is inverted.
57735773
def X86testp_commutable : PatFrag<(ops node:$src1, node:$src2),
57745774
(X86testp node:$src1, node:$src2), [{
5775-
return onlyUsesZeroFlag(Op);
5775+
return onlyUsesZeroFlag(SDValue(N, 0));
57765776
}]>;
57775777

57785778
let Defs = [EFLAGS], Predicates = [HasAVX] in {

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