Skip to content

Commit 5a5811f

Browse files
LiqinWengLiqinWeng
committed
address the comments
1 parent 33b7481 commit 5a5811f

File tree

3 files changed

+38
-49
lines changed

3 files changed

+38
-49
lines changed

‎llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -290,6 +290,7 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
290290
return MILog2SEW;
291291
return 6;
292292
}
293+
293294
// Vector Integer Arithmetic Instructions
294295
// Vector Single-Width Integer Add and Subtract
295296
case RISCV::VADD_VI:

‎llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll‎

Lines changed: 28 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb,+zvfbfwma,+zvfh,+zvfbfmin -riscv-enable-vl-optimizer=false -verify-machineinstrs | FileCheck %s --check-prefixes=NOVLOPT
3-
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb,+zvfbfwma,+zvfh,+zvfbfmin -riscv-enable-vl-optimizer=false -verify-machineinstrs | FileCheck %s --check-prefixes=NOVLOPT
4-
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb,+zvfbfwma,+zvfh,+zvfbfmin -riscv-enable-vl-optimizer -verify-machineinstrs | FileCheck %s --check-prefixes=VLOPT
5-
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb,+zvfbfwma,+zvfh,+zvfbfmin -riscv-enable-vl-optimizer -verify-machineinstrs | FileCheck %s --check-prefixes=VLOPT
2+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb,+zvfbfwma -riscv-enable-vl-optimizer=false -verify-machineinstrs | FileCheck %s --check-prefixes=NOVLOPT
3+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb,+zvfbfwma -riscv-enable-vl-optimizer=false -verify-machineinstrs | FileCheck %s --check-prefixes=NOVLOPT
4+
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvbb,+zvfbfwma -riscv-enable-vl-optimizer -verify-machineinstrs | FileCheck %s --check-prefixes=VLOPT
5+
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvbb,+zvfbfwma -riscv-enable-vl-optimizer -verify-machineinstrs | FileCheck %s --check-prefixes=VLOPT
66

77
; The purpose of this file is to check the behavior of specific instructions as it relates to the VL optimizer
88

@@ -5070,62 +5070,50 @@ define <vscale x 4 x float> @vfwmaccbf16_vf(<vscale x 4 x float> %a, bfloat %b,
50705070
ret <vscale x 4 x float> %2
50715071
}
50725072

5073-
define <vscale x 4 x half> @vfsqrt(<vscale x 4 x half> %a) {
5073+
define <vscale x 4 x double> @vfsqrt(<vscale x 4 x float> %a) {
50745074
; NOVLOPT-LABEL: vfsqrt:
50755075
; NOVLOPT: # %bb.0:
5076-
; NOVLOPT-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5077-
; NOVLOPT-NEXT: vfwcvt.f.f.v v10, v8
50785076
; NOVLOPT-NEXT: fsrmi a0, 0
50795077
; NOVLOPT-NEXT: vsetivli zero, 7, e32, m2, ta, ma
5080-
; NOVLOPT-NEXT: vfsqrt.v v10, v10
5081-
; NOVLOPT-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5082-
; NOVLOPT-NEXT: vfncvt.f.f.w v8, v10
5078+
; NOVLOPT-NEXT: vfsqrt.v v10, v8
50835079
; NOVLOPT-NEXT: fsrm a0
5080+
; NOVLOPT-NEXT: vsetivli zero, 6, e32, m2, ta, ma
5081+
; NOVLOPT-NEXT: vfwmacc.vv v12, v8, v10
5082+
; NOVLOPT-NEXT: vmv4r.v v8, v12
50845083
; NOVLOPT-NEXT: ret
50855084
;
50865085
; VLOPT-LABEL: vfsqrt:
50875086
; VLOPT: # %bb.0:
5088-
; VLOPT-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5089-
; VLOPT-NEXT: vfwcvt.f.f.v v10, v8
50905087
; VLOPT-NEXT: fsrmi a0, 0
5091-
; VLOPT-NEXT: vsetvli zero, zero, e32, m2, ta, ma
5092-
; VLOPT-NEXT: vfsqrt.v v10, v10
5093-
; VLOPT-NEXT: vsetvli zero, zero, e16, m1, ta, ma
5094-
; VLOPT-NEXT: vfncvt.f.f.w v8, v10
5088+
; VLOPT-NEXT: vsetivli zero, 6, e32, m2, ta, ma
5089+
; VLOPT-NEXT: vfsqrt.v v10, v8
50955090
; VLOPT-NEXT: fsrm a0
5091+
; VLOPT-NEXT: vfwmacc.vv v12, v8, v10
5092+
; VLOPT-NEXT: vmv4r.v v8, v12
50965093
; VLOPT-NEXT: ret
5097-
%1 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16(<vscale x 4 x float> poison, <vscale x 4 x half> %a, iXLen 6)
5098-
%2 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, iXLen 0, iXLen 7)
5099-
%3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32(<vscale x 4 x half> poison, <vscale x 4 x float> %2, iXLen 0, iXLen 6)
5100-
ret <vscale x 4 x half> %3
5094+
%1 = call <vscale x 4 x float> @llvm.riscv.vfsqrt.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, iXLen 0, iXLen 7)
5095+
%2 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %1, iXLen 7, iXLen 6, iXLen 0)
5096+
ret <vscale x 4 x double> %2
51015097
}
51025098

5103-
define <vscale x 4 x half> @vfrsqrt7(<vscale x 4 x half> %a) {
5099+
define <vscale x 4 x double> @vfrsqrt7(<vscale x 4 x float> %a) {
51045100
; NOVLOPT-LABEL: vfrsqrt7:
51055101
; NOVLOPT: # %bb.0:
5106-
; NOVLOPT-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5107-
; NOVLOPT-NEXT: vfwcvt.f.f.v v10, v8
51085102
; NOVLOPT-NEXT: vsetivli zero, 7, e32, m2, ta, ma
5109-
; NOVLOPT-NEXT: vfrsqrt7.v v10, v10
5110-
; NOVLOPT-NEXT: fsrmi a0, 0
5111-
; NOVLOPT-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5112-
; NOVLOPT-NEXT: vfncvt.f.f.w v8, v10
5113-
; NOVLOPT-NEXT: fsrm a0
5103+
; NOVLOPT-NEXT: vfrsqrt7.v v10, v8
5104+
; NOVLOPT-NEXT: vsetivli zero, 6, e32, m2, ta, ma
5105+
; NOVLOPT-NEXT: vfwmacc.vv v12, v8, v10
5106+
; NOVLOPT-NEXT: vmv4r.v v8, v12
51145107
; NOVLOPT-NEXT: ret
51155108
;
51165109
; VLOPT-LABEL: vfrsqrt7:
51175110
; VLOPT: # %bb.0:
5118-
; VLOPT-NEXT: vsetivli zero, 6, e16, m1, ta, ma
5119-
; VLOPT-NEXT: vfwcvt.f.f.v v10, v8
5120-
; VLOPT-NEXT: vsetvli zero, zero, e32, m2, ta, ma
5121-
; VLOPT-NEXT: vfrsqrt7.v v10, v10
5122-
; VLOPT-NEXT: fsrmi a0, 0
5123-
; VLOPT-NEXT: vsetvli zero, zero, e16, m1, ta, ma
5124-
; VLOPT-NEXT: vfncvt.f.f.w v8, v10
5125-
; VLOPT-NEXT: fsrm a0
5111+
; VLOPT-NEXT: vsetivli zero, 6, e32, m2, ta, ma
5112+
; VLOPT-NEXT: vfrsqrt7.v v10, v8
5113+
; VLOPT-NEXT: vfwmacc.vv v12, v8, v10
5114+
; VLOPT-NEXT: vmv4r.v v8, v12
51265115
; VLOPT-NEXT: ret
5127-
%1 = call <vscale x 4 x float> @llvm.riscv.vfwcvt.f.f.v.nxv4f32.nxv4f16(<vscale x 4 x float> poison, <vscale x 4 x half> %a, iXLen 6)
5128-
%2 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %1, iXLen 7)
5129-
%3 = call <vscale x 4 x half> @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32(<vscale x 4 x half> poison,<vscale x 4 x float> %2, iXLen 0, iXLen 6)
5130-
ret <vscale x 4 x half> %3
5116+
%1 = call <vscale x 4 x float> @llvm.riscv.vfrsqrt7.nxv4f32(<vscale x 4 x float> poison, <vscale x 4 x float> %a, iXLen 7)
5117+
%2 = call <vscale x 4 x double> @llvm.riscv.vfwmacc(<vscale x 4 x double> poison, <vscale x 4 x float> %a, <vscale x 4 x float> %1, iXLen 7, iXLen 6, iXLen 0)
5118+
ret <vscale x 4 x double> %2
51315119
}

‎llvm/test/CodeGen/RISCV/rvv/vl-opt.mir‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -141,43 +141,43 @@ body: |
141141
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 4 /* e16 */, 0
142142
...
143143
---
144-
name: vfsqrt
144+
name: vfsqrt_nofpexcept
145145
body: |
146146
bb.0:
147-
; CHECK-LABEL: name: vfsqrt
147+
; CHECK-LABEL: name: vfsqrt_nofpexcept
148148
; CHECK: %x:vrm2 = nofpexcept PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 6, 5 /* e32 */, 3 /* ta, ma */, implicit $frm
149149
; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
150150
%x:vrm2 = nofpexcept PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5, 3, implicit $frm
151151
early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4, 3, implicit $frm
152152
...
153153
---
154-
name: vfsqrt_nofpexcept
154+
name: vfsqrt_fpexcept
155155
body: |
156156
bb.0:
157-
; CHECK-LABEL: name: vfsqrt_nofpexcept
157+
; CHECK-LABEL: name: vfsqrt_fpexcept
158158
; CHECK: %x:vrm2 = PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5 /* e32 */, 3 /* ta, ma */, implicit $frm
159159
; CHECK-NEXT: early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4 /* e16 */, 3 /* ta, ma */, implicit $frm
160160
%x:vrm2 = PseudoVFSQRT_V_M2_E32 $noreg, $noreg, 7, 8, 5, 3, implicit $frm
161161
early-clobber %y:vr = nofpexcept PseudoVFNCVTBF16_F_F_W_M1_E16 $noreg, %x, 7, 6, 4, 3, implicit $frm
162162
...
163163
---
164-
name: vfrsqrt7
164+
name: vfrsqrt7_nofpexcept
165165
body: |
166166
bb.0:
167-
; CHECK-LABEL: name: vfrsqrt7
167+
; CHECK-LABEL: name: vfrsqrt7_nofpexcept
168168
; CHECK: %x:vrm2 = nofpexcept PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
169169
; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
170170
%x:vrm2 = nofpexcept PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5, 0
171171
%y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
172172
...
173173
---
174-
name: vfrsqrt7_nofpexcept
174+
name: vfrsqrt7_fpexcept
175175
body: |
176176
bb.0:
177-
; CHECK-LABEL: name: vfrsqrt7_nofpexcept
177+
; CHECK-LABEL: name: vfrsqrt7_fpexcept
178178
; CHECK: %x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5 /* e32 */, 0 /* tu, mu */
179179
; CHECK-NEXT: %y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
180-
%x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5, 0
180+
%x:vrm2 = PseudoVFRSQRT7_V_M2_E32 $noreg, $noreg, 7, 5, 0
181181
%y:vrm2 = PseudoVADD_VV_M2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
182182
...
183183
---

0 commit comments

Comments
 (0)