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daniilavdeevdaniilavdeev
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[RISCV][NFC] refactor CFI emitting
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2 files changed

+114
-99
lines changed

2 files changed

+114
-99
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp‎

Lines changed: 111 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,102 @@
2727

2828
using namespace llvm;
2929

30+
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
31+
return RISCV::VRRegClass.contains(BaseReg) ? 1
32+
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
33+
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
34+
: 8;
35+
}
36+
37+
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
38+
const Register &Reg) {
39+
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
40+
// If it's not a grouped vector register, it doesn't have subregister, so
41+
// the base register is just itself.
42+
if (BaseReg == RISCV::NoRegister)
43+
BaseReg = Reg;
44+
return BaseReg;
45+
}
46+
47+
namespace {
48+
49+
struct CFIRestoreRegisterEmitter {
50+
CFIRestoreRegisterEmitter(MachineFunction &, const RISCVSubtarget &) {};
51+
52+
void emit(MachineFunction &MF, MachineBasicBlock &MBB,
53+
MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
54+
const RISCVInstrInfo &TII, const DebugLoc &DL,
55+
const CalleeSavedInfo &CS) const {
56+
Register Reg = CS.getReg();
57+
unsigned CFIIndex = MF.addFrameInst(
58+
MCCFIInstruction::createRestore(nullptr, RI.getDwarfRegNum(Reg, true)));
59+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
60+
.addCFIIndex(CFIIndex)
61+
.setMIFlag(MachineInstr::FrameDestroy);
62+
}
63+
};
64+
65+
class CFIStoreRegisterEmitter {
66+
MachineFrameInfo &MFI;
67+
68+
public:
69+
CFIStoreRegisterEmitter(MachineFunction &MF, const RISCVSubtarget &)
70+
: MFI{MF.getFrameInfo()} {};
71+
72+
void emit(MachineFunction &MF, MachineBasicBlock &MBB,
73+
MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
74+
const RISCVInstrInfo &TII, const DebugLoc &DL,
75+
const CalleeSavedInfo &CS) const {
76+
int FrameIdx = CS.getFrameIdx();
77+
int64_t Offset = MFI.getObjectOffset(FrameIdx);
78+
Register Reg = CS.getReg();
79+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
80+
nullptr, RI.getDwarfRegNum(Reg, true), Offset));
81+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
82+
.addCFIIndex(CFIIndex)
83+
.setMIFlag(MachineInstr::FrameSetup);
84+
}
85+
};
86+
87+
class CFIRestoreRVVRegisterEmitter {
88+
const llvm::RISCVRegisterInfo *TRI;
89+
90+
public:
91+
CFIRestoreRVVRegisterEmitter(MachineFunction &, const RISCVSubtarget &STI)
92+
: TRI{STI.getRegisterInfo()} {};
93+
94+
void emit(MachineFunction &MF, MachineBasicBlock &MBB,
95+
MachineBasicBlock::iterator MBBI, const RISCVRegisterInfo &RI,
96+
const RISCVInstrInfo &TII, const DebugLoc &DL,
97+
const CalleeSavedInfo &CS) const {
98+
MCRegister BaseReg = getRVVBaseRegister(*TRI, CS.getReg());
99+
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
100+
for (unsigned i = 0; i < NumRegs; ++i) {
101+
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
102+
nullptr, RI.getDwarfRegNum(BaseReg + i, true)));
103+
BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
104+
.addCFIIndex(CFIIndex)
105+
.setMIFlag(MachineInstr::FrameDestroy);
106+
}
107+
}
108+
};
109+
110+
} // namespace
111+
112+
template <typename Emitter>
113+
void RISCVFrameLowering::emitCFIForCSI(
114+
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
115+
const SmallVector<CalleeSavedInfo, 8> &CSI) const {
116+
MachineFunction *MF = MBB.getParent();
117+
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
118+
const RISCVInstrInfo *TII = STI.getInstrInfo();
119+
DebugLoc DL = MBB.findDebugLoc(MBBI);
120+
121+
Emitter E{*MF, STI};
122+
for (const auto &CS : CSI)
123+
E.emit(*MF, MBB, MBBI, *RI, *TII, DL, CS);
124+
}
125+
30126
static Align getABIStackAlignment(RISCVABI::ABI ABI) {
31127
if (ABI == RISCVABI::ABI_ILP32E)
32128
return Align(4);
@@ -610,16 +706,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
610706
.addCFIIndex(CFIIndex)
611707
.setMIFlag(MachineInstr::FrameSetup);
612708

613-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
614-
int FrameIdx = Entry.getFrameIdx();
615-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
616-
Register Reg = Entry.getReg();
617-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
618-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
619-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
620-
.addCFIIndex(CFIIndex)
621-
.setMIFlag(MachineInstr::FrameSetup);
622-
}
709+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
710+
getPushOrLibCallsSavedInfo(MF, CSI));
623711
}
624712

625713
// FIXME (note copied from Lanai): This appears to be overallocating. Needs
@@ -661,16 +749,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
661749
.addCFIIndex(CFIIndex)
662750
.setMIFlag(MachineInstr::FrameSetup);
663751

664-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
665-
int FrameIdx = Entry.getFrameIdx();
666-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
667-
Register Reg = Entry.getReg();
668-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
669-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
670-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
671-
.addCFIIndex(CFIIndex)
672-
.setMIFlag(MachineInstr::FrameSetup);
673-
}
752+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI,
753+
getPushOrLibCallsSavedInfo(MF, CSI));
674754
}
675755

676756
if (StackSize != 0) {
@@ -697,20 +777,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
697777

698778
// Iterate over list of callee-saved registers and emit .cfi_offset
699779
// directives.
700-
for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
701-
int FrameIdx = Entry.getFrameIdx();
702-
if (FrameIdx >= 0 &&
703-
MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
704-
continue;
705-
706-
int64_t Offset = MFI.getObjectOffset(FrameIdx);
707-
Register Reg = Entry.getReg();
708-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
709-
nullptr, RI->getDwarfRegNum(Reg, true), Offset));
710-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
711-
.addCFIIndex(CFIIndex)
712-
.setMIFlag(MachineInstr::FrameSetup);
713-
}
780+
emitCFIForCSI<CFIStoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
714781

715782
// Generate new FP.
716783
if (hasFP(MF)) {
@@ -895,7 +962,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
895962
.setMIFlag(MachineInstr::FrameDestroy);
896963
}
897964

898-
emitCalleeSavedRVVEpilogCFI(MBB, LastFrameDestroy);
965+
emitCFIForCSI<CFIRestoreRVVRegisterEmitter>(MBB, LastFrameDestroy,
966+
getRVVCalleeSavedInfo(MF, CSI));
899967
}
900968

901969
if (FirstSPAdjustAmount) {
@@ -960,14 +1028,7 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9601028
}
9611029

9621030
// Recover callee-saved registers.
963-
for (const auto &Entry : getUnmanagedCSI(MF, CSI)) {
964-
Register Reg = Entry.getReg();
965-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
966-
nullptr, RI->getDwarfRegNum(Reg, true)));
967-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
968-
.addCFIIndex(CFIIndex)
969-
.setMIFlag(MachineInstr::FrameDestroy);
970-
}
1031+
emitCFIForCSI<CFIRestoreRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));
9711032

9721033
bool ApplyPop = RVFI->isPushable(MF) && MBBI != MBB.end() &&
9731034
MBBI->getOpcode() == RISCV::CM_POP;
@@ -976,7 +1037,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9761037
// space. Align the stack size down to a multiple of 16. This is needed for
9771038
// RVE.
9781039
// FIXME: Can we increase the stack size to a multiple of 16 instead?
979-
uint64_t Spimm = std::min(alignDown(StackSize, 16), (uint64_t)48);
1040+
uint64_t Spimm =
1041+
std::min(alignDown(StackSize, 16), static_cast<uint64_t>(48));
9801042
MBBI->getOperand(1).setImm(Spimm);
9811043
StackSize -= Spimm;
9821044

@@ -988,14 +1050,8 @@ void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
9881050
if (NextI == MBB.end() || NextI->getOpcode() != RISCV::PseudoRET) {
9891051
++MBBI;
9901052

991-
for (const auto &Entry : getPushOrLibCallsSavedInfo(MF, CSI)) {
992-
Register Reg = Entry.getReg();
993-
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
994-
nullptr, RI->getDwarfRegNum(Reg, true)));
995-
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
996-
.addCFIIndex(CFIIndex)
997-
.setMIFlag(MachineInstr::FrameDestroy);
998-
}
1053+
emitCFIForCSI<CFIRestoreRegisterEmitter>(
1054+
MBB, MBBI, getPushOrLibCallsSavedInfo(MF, CSI));
9991055

10001056
// Update CFA offset. After CM_POP SP should be equal to CFA, so CFA
10011057
// offset should be a zero.
@@ -1695,23 +1751,6 @@ bool RISCVFrameLowering::spillCalleeSavedRegisters(
16951751
return true;
16961752
}
16971753

1698-
static unsigned getCaleeSavedRVVNumRegs(const Register &BaseReg) {
1699-
return RISCV::VRRegClass.contains(BaseReg) ? 1
1700-
: RISCV::VRM2RegClass.contains(BaseReg) ? 2
1701-
: RISCV::VRM4RegClass.contains(BaseReg) ? 4
1702-
: 8;
1703-
}
1704-
1705-
static MCRegister getRVVBaseRegister(const RISCVRegisterInfo &TRI,
1706-
const Register &Reg) {
1707-
MCRegister BaseReg = TRI.getSubReg(Reg, RISCV::sub_vrm1_0);
1708-
// If it's not a grouped vector register, it doesn't have subregister, so
1709-
// the base register is just itself.
1710-
if (BaseReg == RISCV::NoRegister)
1711-
BaseReg = Reg;
1712-
return BaseReg;
1713-
}
1714-
17151754
void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17161755
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, bool HasFP) const {
17171756
MachineFunction *MF = MBB.getParent();
@@ -1737,39 +1776,14 @@ void RISCVFrameLowering::emitCalleeSavedRVVPrologCFI(
17371776
for (auto &CS : RVVCSI) {
17381777
// Insert the spill to the stack frame.
17391778
int FI = CS.getFrameIdx();
1740-
if (FI >= 0 && MFI.getStackID(FI) == TargetStackID::ScalableVector) {
1741-
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
1742-
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
1743-
for (unsigned i = 0; i < NumRegs; ++i) {
1744-
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1745-
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
1746-
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
1747-
.addCFIIndex(CFIIndex)
1748-
.setMIFlag(MachineInstr::FrameSetup);
1749-
}
1750-
}
1751-
}
1752-
}
1753-
1754-
void RISCVFrameLowering::emitCalleeSavedRVVEpilogCFI(
1755-
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const {
1756-
MachineFunction *MF = MBB.getParent();
1757-
const MachineFrameInfo &MFI = MF->getFrameInfo();
1758-
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
1759-
const TargetInstrInfo &TII = *STI.getInstrInfo();
1760-
const RISCVRegisterInfo &TRI = *STI.getRegisterInfo();
1761-
DebugLoc DL = MBB.findDebugLoc(MI);
1762-
1763-
const auto &RVVCSI = getRVVCalleeSavedInfo(*MF, MFI.getCalleeSavedInfo());
1764-
for (auto &CS : RVVCSI) {
17651779
MCRegister BaseReg = getRVVBaseRegister(TRI, CS.getReg());
17661780
unsigned NumRegs = getCaleeSavedRVVNumRegs(CS.getReg());
17671781
for (unsigned i = 0; i < NumRegs; ++i) {
1768-
unsigned CFIIndex = MF->addFrameInst(MCCFIInstruction::createRestore(
1769-
nullptr, RI->getDwarfRegNum(BaseReg + i, true)));
1782+
unsigned CFIIndex = MF->addFrameInst(createDefCFAOffset(
1783+
TRI, BaseReg + i, -FixedSize, MFI.getObjectOffset(FI) / 8 + i));
17701784
BuildMI(MBB, MI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
17711785
.addCFIIndex(CFIIndex)
1772-
.setMIFlag(MachineInstr::FrameDestroy);
1786+
.setMIFlag(MachineInstr::FrameSetup);
17731787
}
17741788
}
17751789
}

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,11 +91,12 @@ class RISCVFrameLowering : public TargetFrameLowering {
9191
void emitCalleeSavedRVVPrologCFI(MachineBasicBlock &MBB,
9292
MachineBasicBlock::iterator MI,
9393
bool HasFP) const;
94-
void emitCalleeSavedRVVEpilogCFI(MachineBasicBlock &MBB,
95-
MachineBasicBlock::iterator MI) const;
9694
void deallocateStack(MachineFunction &MF, MachineBasicBlock &MBB,
9795
MachineBasicBlock::iterator MBBI, const DebugLoc &DL,
9896
uint64_t &StackSize, int64_t CFAOffset) const;
97+
template <typename Emitter>
98+
void emitCFIForCSI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
99+
const SmallVector<CalleeSavedInfo, 8> &CSI) const;
99100

100101
std::pair<int64_t, Align>
101102
assignRVVStackObjectOffsets(MachineFunction &MF) const;

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