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[NFC] Remove invalid features from test and autogenerate checks. (#124130)
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‎clang/test/CodeGen/AArch64/cpu-supports-target.c

Lines changed: 189 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,44 +1,213 @@
1+
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-attributes --check-globals all --version 5
12
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
23

3-
int check_all_feature() {
4+
//.
5+
// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
6+
//.
7+
// CHECK: Function Attrs: noinline nounwind optnone
8+
// CHECK-LABEL: define dso_local i32 @check_all_features(
9+
// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
10+
// CHECK-NEXT: [[ENTRY:.*:]]
11+
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
12+
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
13+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 66367
14+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66367
15+
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
16+
// CHECK-NEXT: br i1 [[TMP3]], label %[[IF_THEN:.*]], label %[[IF_ELSE:.*]]
17+
// CHECK: [[IF_THEN]]:
18+
// CHECK-NEXT: store i32 1, ptr [[RETVAL]], align 4
19+
// CHECK-NEXT: br label %[[RETURN:.*]]
20+
// CHECK: [[IF_ELSE]]:
21+
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
22+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 14272
23+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 14272
24+
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
25+
// CHECK-NEXT: br i1 [[TMP7]], label %[[IF_THEN1:.*]], label %[[IF_ELSE2:.*]]
26+
// CHECK: [[IF_THEN1]]:
27+
// CHECK-NEXT: store i32 2, ptr [[RETVAL]], align 4
28+
// CHECK-NEXT: br label %[[RETURN]]
29+
// CHECK: [[IF_ELSE2]]:
30+
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
31+
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 2065152
32+
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 2065152
33+
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
34+
// CHECK-NEXT: br i1 [[TMP11]], label %[[IF_THEN3:.*]], label %[[IF_ELSE4:.*]]
35+
// CHECK: [[IF_THEN3]]:
36+
// CHECK-NEXT: store i32 3, ptr [[RETVAL]], align 4
37+
// CHECK-NEXT: br label %[[RETURN]]
38+
// CHECK: [[IF_ELSE4]]:
39+
// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
40+
// CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 288230376183169792
41+
// CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 288230376183169792
42+
// CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]]
43+
// CHECK-NEXT: br i1 [[TMP15]], label %[[IF_THEN5:.*]], label %[[IF_ELSE6:.*]]
44+
// CHECK: [[IF_THEN5]]:
45+
// CHECK-NEXT: store i32 4, ptr [[RETVAL]], align 4
46+
// CHECK-NEXT: br label %[[RETURN]]
47+
// CHECK: [[IF_ELSE6]]:
48+
// CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
49+
// CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 1275134720
50+
// CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1275134720
51+
// CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]]
52+
// CHECK-NEXT: br i1 [[TMP19]], label %[[IF_THEN7:.*]], label %[[IF_ELSE8:.*]]
53+
// CHECK: [[IF_THEN7]]:
54+
// CHECK-NEXT: store i32 5, ptr [[RETVAL]], align 4
55+
// CHECK-NEXT: br label %[[RETURN]]
56+
// CHECK: [[IF_ELSE8]]:
57+
// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
58+
// CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 52814742272
59+
// CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 52814742272
60+
// CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]]
61+
// CHECK-NEXT: br i1 [[TMP23]], label %[[IF_THEN9:.*]], label %[[IF_ELSE10:.*]]
62+
// CHECK: [[IF_THEN9]]:
63+
// CHECK-NEXT: store i32 6, ptr [[RETVAL]], align 4
64+
// CHECK-NEXT: br label %[[RETURN]]
65+
// CHECK: [[IF_ELSE10]]:
66+
// CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
67+
// CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 344671224576
68+
// CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 344671224576
69+
// CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]]
70+
// CHECK-NEXT: br i1 [[TMP27]], label %[[IF_THEN11:.*]], label %[[IF_ELSE12:.*]]
71+
// CHECK: [[IF_THEN11]]:
72+
// CHECK-NEXT: store i32 7, ptr [[RETVAL]], align 4
73+
// CHECK-NEXT: br label %[[RETURN]]
74+
// CHECK: [[IF_ELSE12]]:
75+
// CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
76+
// CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 3918083994400
77+
// CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 3918083994400
78+
// CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]]
79+
// CHECK-NEXT: br i1 [[TMP31]], label %[[IF_THEN13:.*]], label %[[IF_ELSE14:.*]]
80+
// CHECK: [[IF_THEN13]]:
81+
// CHECK-NEXT: store i32 8, ptr [[RETVAL]], align 4
82+
// CHECK-NEXT: br label %[[RETURN]]
83+
// CHECK: [[IF_ELSE14]]:
84+
// CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
85+
// CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 92359111017216
86+
// CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 92359111017216
87+
// CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]]
88+
// CHECK-NEXT: br i1 [[TMP35]], label %[[IF_THEN15:.*]], label %[[IF_ELSE16:.*]]
89+
// CHECK: [[IF_THEN15]]:
90+
// CHECK-NEXT: store i32 9, ptr [[RETVAL]], align 4
91+
// CHECK-NEXT: br label %[[RETURN]]
92+
// CHECK: [[IF_ELSE16]]:
93+
// CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
94+
// CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 10836786603360256
95+
// CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 10836786603360256
96+
// CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]]
97+
// CHECK-NEXT: br i1 [[TMP39]], label %[[IF_THEN17:.*]], label %[[IF_ELSE18:.*]]
98+
// CHECK: [[IF_THEN17]]:
99+
// CHECK-NEXT: store i32 10, ptr [[RETVAL]], align 4
100+
// CHECK-NEXT: br label %[[RETURN]]
101+
// CHECK: [[IF_ELSE18]]:
102+
// CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
103+
// CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 54047593709241088
104+
// CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 54047593709241088
105+
// CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]]
106+
// CHECK-NEXT: br i1 [[TMP43]], label %[[IF_THEN19:.*]], label %[[IF_ELSE20:.*]]
107+
// CHECK: [[IF_THEN19]]:
108+
// CHECK-NEXT: store i32 11, ptr [[RETVAL]], align 4
109+
// CHECK-NEXT: br label %[[RETURN]]
110+
// CHECK: [[IF_ELSE20]]:
111+
// CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
112+
// CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 216177180294578944
113+
// CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 216177180294578944
114+
// CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]]
115+
// CHECK-NEXT: br i1 [[TMP47]], label %[[IF_THEN21:.*]], label %[[IF_ELSE22:.*]]
116+
// CHECK: [[IF_THEN21]]:
117+
// CHECK-NEXT: store i32 12, ptr [[RETVAL]], align 4
118+
// CHECK-NEXT: br label %[[RETURN]]
119+
// CHECK: [[IF_ELSE22]]:
120+
// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
121+
// CHECK-NEXT: br label %[[RETURN]]
122+
// CHECK: [[RETURN]]:
123+
// CHECK-NEXT: [[TMP48:%.*]] = load i32, ptr [[RETVAL]], align 4
124+
// CHECK-NEXT: ret i32 [[TMP48]]
125+
//
126+
int check_all_features() {
4127
if (__builtin_cpu_supports("rng+flagm+flagm2+fp16fml+dotprod+sm4"))
5128
return 1;
6-
else if (__builtin_cpu_supports("rdm+lse+fp+simd+crc+sha1+sha2+sha3"))
129+
else if (__builtin_cpu_supports("rdm+lse+fp+simd+crc+sha2+sha3"))
7130
return 2;
8-
else if (__builtin_cpu_supports("aes+pmull+fp16+dit+dpb+dpb2+jscvt"))
131+
else if (__builtin_cpu_supports("aes+fp16+dit+dpb+dpb2+jscvt"))
9132
return 3;
10133
else if (__builtin_cpu_supports("fcma+rcpc+rcpc2+rcpc3+frintts"))
11134
return 4;
12135
else if (__builtin_cpu_supports("i8mm+bf16+sve"))
13136
return 5;
14-
else if (__builtin_cpu_supports("sve+ebf16+i8mm+f32mm+f64mm"))
137+
else if (__builtin_cpu_supports("sve+bf16+i8mm+f32mm+f64mm"))
15138
return 6;
16-
else if (__builtin_cpu_supports("sve2+sve2-aes+sve2-pmull128"))
139+
else if (__builtin_cpu_supports("sve2+sve2-aes"))
17140
return 7;
18141
else if (__builtin_cpu_supports("sve2-bitperm+sve2-sha3+sve2-sm4"))
19142
return 8;
20143
else if (__builtin_cpu_supports("sme+memtag+sb"))
21144
return 9;
22-
else if (__builtin_cpu_supports("predres+ssbs+ssbs2+bti+ls64+ls64_v"))
145+
else if (__builtin_cpu_supports("predres+ssbs+bti+ls64"))
23146
return 10;
24-
else if (__builtin_cpu_supports("ls64_accdata+wfxt+sme-f64f64"))
147+
else if (__builtin_cpu_supports("wfxt+sme-f64f64"))
25148
return 11;
26149
else if (__builtin_cpu_supports("sme-i16i64+sme2"))
27150
return 12;
28151
else
29152
return 0;
30153
}
31154

32-
// CHECK-LABEL: define dso_local i32 @neon_code() #1
155+
// CHECK: Function Attrs: noinline nounwind optnone
156+
// CHECK-LABEL: define dso_local i32 @neon_code(
157+
// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
158+
// CHECK-NEXT: [[ENTRY:.*:]]
159+
// CHECK-NEXT: ret i32 1
160+
//
33161
int __attribute__((target("simd"))) neon_code() { return 1; }
34162

35-
// CHECK-LABEL: define dso_local i32 @sve_code() #2
163+
// CHECK: Function Attrs: noinline nounwind optnone
164+
// CHECK-LABEL: define dso_local i32 @sve_code(
165+
// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
166+
// CHECK-NEXT: [[ENTRY:.*:]]
167+
// CHECK-NEXT: ret i32 2
168+
//
36169
int __attribute__((target("sve"))) sve_code() { return 2; }
37170

38-
// CHECK-LABEL: define dso_local i32 @code() #0
171+
// CHECK: Function Attrs: noinline nounwind optnone
172+
// CHECK-LABEL: define dso_local i32 @code(
173+
// CHECK-SAME: ) #[[ATTR0]] {
174+
// CHECK-NEXT: [[ENTRY:.*:]]
175+
// CHECK-NEXT: ret i32 3
176+
//
39177
int code() { return 3; }
40178

41-
// CHECK-LABEL: define dso_local i32 @test_versions() #0
179+
// CHECK: Function Attrs: noinline nounwind optnone
180+
// CHECK-LABEL: define dso_local i32 @test_versions(
181+
// CHECK-SAME: ) #[[ATTR0]] {
182+
// CHECK-NEXT: [[ENTRY:.*:]]
183+
// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
184+
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
185+
// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1073807616
186+
// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073807616
187+
// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
188+
// CHECK-NEXT: br i1 [[TMP3]], label %[[IF_THEN:.*]], label %[[IF_ELSE:.*]]
189+
// CHECK: [[IF_THEN]]:
190+
// CHECK-NEXT: [[CALL:%.*]] = call i32 @sve_code()
191+
// CHECK-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
192+
// CHECK-NEXT: br label %[[RETURN:.*]]
193+
// CHECK: [[IF_ELSE]]:
194+
// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
195+
// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 768
196+
// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 768
197+
// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
198+
// CHECK-NEXT: br i1 [[TMP7]], label %[[IF_THEN1:.*]], label %[[IF_ELSE3:.*]]
199+
// CHECK: [[IF_THEN1]]:
200+
// CHECK-NEXT: [[CALL2:%.*]] = call i32 @neon_code()
201+
// CHECK-NEXT: store i32 [[CALL2]], ptr [[RETVAL]], align 4
202+
// CHECK-NEXT: br label %[[RETURN]]
203+
// CHECK: [[IF_ELSE3]]:
204+
// CHECK-NEXT: [[CALL4:%.*]] = call i32 @code()
205+
// CHECK-NEXT: store i32 [[CALL4]], ptr [[RETVAL]], align 4
206+
// CHECK-NEXT: br label %[[RETURN]]
207+
// CHECK: [[RETURN]]:
208+
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4
209+
// CHECK-NEXT: ret i32 [[TMP8]]
210+
//
42211
int test_versions() {
43212
if (__builtin_cpu_supports("sve"))
44213
return sve_code();
@@ -47,6 +216,12 @@ int test_versions() {
47216
else
48217
return code();
49218
}
50-
// CHECK: attributes #0 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
51-
// CHECK: attributes #1 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
52-
// CHECK: attributes #2 = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
219+
220+
//.
221+
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
222+
// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+neon" }
223+
// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+fp-armv8,+fullfp16,+sve" }
224+
//.
225+
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
226+
// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
227+
//.

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