Try to infer register class for physical register defs

Author: s-barannikov

llvm/include/llvm/Target/Target.td

@@ -283,6 +283,8 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // value means copying is extremely expensive or impossible.
   int CopyCost = 1;
 
+  RegisterClass CrossCopyRegClass = ?;
+
   // MemberList - Specify which registers are in this class.  If the
   // allocation_order_* method are not specified, this also defines the order of
   // allocation used by the register allocator.

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

@@ -362,13 +362,6 @@ foreach Index = 0...255 in {
 //  Groupings using register classes and tuples
 //===----------------------------------------------------------------------===//
 
-def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
-  let CopyCost = -1;
-  let isAllocatable = 0;
-  let HasSGPR = 1;
-  let BaseClassOrder = 10000;
-}
-
 def M0_CLASS : SIRegisterClass<"AMDGPU", [i32], 32, (add M0)> {
   let CopyCost = 1;
   let isAllocatable = 0;
@@ -801,6 +794,14 @@ def SReg_32_XM0 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2
 
 } // End GeneratePressureSet = 0
 
+def SCC_CLASS : SIRegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
+  let CopyCost = -1;
+  let isAllocatable = 0;
+  let CrossCopyRegClass = SReg_32_XM0_XEXEC;
+  let HasSGPR = 1;
+  let BaseClassOrder = 10000;
+}
+
 // Register class for all scalar registers (SGPRs + Special Registers)
 def SReg_32 : SIRegisterClass<"AMDGPU", [i32, f32, i16, f16, bf16, v2i16, v2f16, v2bf16, i1], 32,
   (add SReg_32_XM0, M0_CLASS)> {

llvm/utils/TableGen/Common/CodeGenRegisters.cpp

@@ -1306,6 +1306,18 @@ CodeGenRegBank::CodeGenRegBank(const RecordKeeper &Records,
       addToMaps(&RC);
   }
 
+  // Resolve cross references.
+  for (const Record *RCRec : RCs) {
+    if (const Record *CrossCopyRCRec =
+            RCRec->getValueAsOptionalDef("CrossCopyRegClass")) {
+      const CodeGenRegisterClass *CrossCopyRC = getRegClass(CrossCopyRCRec);
+      if (!CrossCopyRC->Allocatable)
+        PrintFatalError(RCRec->getFieldLoc("CrossCopyRegClass"),
+                        "cross-copy register class must be allocatable");
+      getRegClass(RCRec)->CrossCopyRC = CrossCopyRC;
+    }
+  }
+
   // Infer missing classes to create a full algebra.
   computeInferredRegisterClasses();
 

llvm/utils/TableGen/Common/CodeGenRegisters.h

@@ -351,6 +351,7 @@ class CodeGenRegisterClass {
   RegSizeInfoByHwMode RSI;
   int CopyCost;
   bool Allocatable;
+  const CodeGenRegisterClass *CrossCopyRC = nullptr;
   StringRef AltOrderSelect;
   uint8_t AllocationPriority;
   bool GlobalPriority;

llvm/utils/TableGen/GlobalISelEmitter.cpp

@@ -1570,6 +1570,17 @@ Expected<action_iterator> GlobalISelEmitter::importDefRenderers(
     StringRef PermanentRef = M.getOperandMatcher(OpName).getSymbolicName();
     CopyBuilder.addRenderer<CopyRenderer>(PermanentRef);
     CopyBuilder.addRenderer<AddRegisterRenderer>(Target, Reg);
+
+    const CodeGenRegisterClass *RC = CGRegs.getRegClassForRegister(Reg);
+    if (RC && !RC->Allocatable)
+      RC = RC->CrossCopyRC;
+
+    if (!RC)
+      return failedImport("could not infer register class for " +
+                          Reg->getName());
+
+    M.addAction<ConstrainOperandToRegClassAction>(CopyBuilder.getInsnID(),
+                                                  /*OpIdx=*/0, *RC);
   }
 
   return InsertPt;