Fixups

Author: MacDue

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -22514,20 +22514,18 @@ static SDValue performSTNT1Combine(SDNode *N, SelectionDAG &DAG) {
 ///   movi v0.2d, #0
 ///   str q0, [x0]
 ///
-static SDValue replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St,
-                                      AArch64Subtarget const &Subtarget) {
+static SDValue replaceZeroVectorStore(SelectionDAG &DAG, StoreSDNode &St) {
   SDValue StVal = St.getValue();
   EVT VT = StVal.getValueType();
 
   // Avoid scalarizing zero splat stores for scalable vectors.
   if (VT.isScalableVector())
     return SDValue();
 
-  // Do not replace the FP store when it could result in a streaming memory
+  // Do not replace the vector store when it could result in a streaming memory
   // hazard.
-  if (VT.getVectorElementType().isFloatingPoint() &&
-      Subtarget.getStreamingHazardSize() > 0 &&
-      (Subtarget.isStreaming() || Subtarget.isStreamingCompatible()))
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  if (!TLI.canUseIntLoadStoreForFloatValues())
     return SDValue();
 
   // It is beneficial to scalarize a zero splat store for 2 or 3 i64 elements or
@@ -22659,7 +22657,7 @@ static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   // If we get a splat of zeros, convert this vector store to a store of
   // scalars. They will be merged into store pairs of xzr thereby removing one
   // instruction and one register.
-  if (SDValue ReplacedZeroSplat = replaceZeroVectorStore(DAG, *S, *Subtarget))
+  if (SDValue ReplacedZeroSplat = replaceZeroVectorStore(DAG, *S))
     return ReplacedZeroSplat;
 
   // FIXME: The logic for deciding if an unaligned store should be split should

llvm/test/CodeGen/AArch64/sve-streaming-mode-fp-constant-stores.ll

@@ -25,6 +25,21 @@ entry:
   ret void
 }
 
+; (Integer types still use GPR stores)
+define void @store_i64_0(ptr %num) {
+; CHECK-LABEL: store_i64_0:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    str xzr, [x0]
+; CHECK-NEXT:    ret
+;
+; NOHAZARD-LABEL: store_i64_0:
+; NOHAZARD:       // %bb.0:
+; NOHAZARD-NEXT:    str xzr, [x0]
+; NOHAZARD-NEXT:    ret
+  store i64 0, ptr %num, align 8
+  ret void
+}
+
 define void @"store_f64_1.0"(ptr %num) {
 ; CHECK-LABEL: store_f64_1.0:
 ; CHECK:       // %bb.0: // %entry
@@ -45,8 +60,8 @@ entry:
 define void @"store_f64_1.23456789"(ptr %num) {
 ; CHECK-LABEL: store_f64_1.23456789:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    adrp x8, .LCPI2_0
-; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI2_0]
+; CHECK-NEXT:    adrp x8, .LCPI3_0
+; CHECK-NEXT:    ldr d0, [x8, :lo12:.LCPI3_0]
 ; CHECK-NEXT:    str d0, [x0]
 ; CHECK-NEXT:    ret
 ;