Merge remote-tracking branch 'origin/main' into vplan-simplify-branch-on-const-entry

Author: fhahn

bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp

@@ -2517,10 +2517,8 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
   createInstrIncMemory(const MCSymbol *Target, MCContext *Ctx, bool IsLeaf,
                        unsigned CodePointerSize) const override {
     unsigned int I = 0;
-    InstructionListType Instrs(IsLeaf ? 12 : 10);
+    InstructionListType Instrs(10);
 
-    if (IsLeaf)
-      createStackPointerIncrement(Instrs[I++], 128);
     createPushRegisters(Instrs[I++], AArch64::X0, AArch64::X1);
     getSystemFlag(Instrs[I++], AArch64::X1);
     InstructionListType Addr = materializeAddress(Target, Ctx, AArch64::X0);
@@ -2535,8 +2533,6 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
     loadReg(Instrs[I++], AArch64::X2, AArch64::SP);
     setSystemFlag(Instrs[I++], AArch64::X1);
     createPopRegisters(Instrs[I++], AArch64::X0, AArch64::X1);
-    if (IsLeaf)
-      createStackPointerDecrement(Instrs[I++], 128);
     return Instrs;
   }
 

clang/include/clang/Basic/AttrDocs.td

@@ -3752,45 +3752,45 @@ functions intended for different purposes have distinct CFI identities.
 
   // Header file - define convenience macros
   #define __cfi_salt(s) __attribute__((cfi_salt(s)))
-  
+
   // Typedef for regular function pointers
   typedef int (*fptr_t)(void);
-  
-  // Typedef for salted function pointers  
+
+  // Typedef for salted function pointers
   typedef int (*fptr_salted_t)(void) __cfi_salt("pepper");
-  
+
   struct widget_ops {
     fptr_t init;          // Regular CFI
     fptr_salted_t exec;   // Salted CFI
     fptr_t cleanup;       // Regular CFI
   };
-  
+
   // Function implementations
   static int widget_init(void) { return 0; }
   static int widget_exec(void) __cfi_salt("pepper") { return 1; }
   static int widget_cleanup(void) { return 0; }
-  
+
   static struct widget_ops ops = {
     .init = widget_init,      // OK - compatible types
     .exec = widget_exec,      // OK - both use "pepper" salt
     .cleanup = widget_cleanup // OK - compatible types
   };
-  
+
   // Using C++11 attribute syntax
   void secure_callback(void) [[clang::cfi_salt("secure")]];
-  
+
   // This would cause a compilation error:
   // fptr_t bad_ptr = widget_exec;  // Error: incompatible types
 
 **Notes:**
 
 * The salt string can contain non-NULL ASCII characters, including spaces and
   quotes
-* This attribute only applies to function types; using it on non-function 
+* This attribute only applies to function types; using it on non-function
   types will generate a warning
-* All declarations and definitions of the same function must use identical 
+* All declarations and definitions of the same function must use identical
   salt values
-* The attribute affects type compatibility during compilation and CFI hash 
+* The attribute affects type compatibility during compilation and CFI hash
   generation during code generation
   }];
 }

clang/include/clang/CIR/Dialect/IR/CIRDataLayout.h

@@ -68,6 +68,18 @@ class CIRDataLayout {
     return llvm::alignTo(getTypeStoreSize(ty), getABITypeAlign(ty).value());
   }
 
+  /// Returns the offset in bits between successive objects of the
+  /// specified type, including alignment padding; always a multiple of 8.
+  ///
+  /// If Ty is a scalable vector type, the scalable property will be set and
+  /// the runtime size will be a positive integer multiple of the base size.
+  ///
+  /// This is the amount that alloca reserves for this type. For example,
+  /// returns 96 or 128 for x86_fp80, depending on alignment.
+  llvm::TypeSize getTypeAllocSizeInBits(mlir::Type ty) const {
+    return 8 * getTypeAllocSize(ty);
+  }
+
   llvm::TypeSize getTypeSizeInBits(mlir::Type ty) const;
 };
 

clang/include/clang/CIR/MissingFeatures.h

@@ -146,7 +146,6 @@ struct MissingFeatures {
   static bool cxxabiUseARMMethodPtrABI() { return false; }
   static bool cxxabiUseARMGuardVarABI() { return false; }
   static bool cxxabiAppleARM64CXXABI() { return false; }
-  static bool isDiscreteBitFieldABI() { return false; }
 
   // Address class
   static bool addressOffset() { return false; }

clang/include/clang/Sema/Sema.h

@@ -5363,7 +5363,7 @@ class Sema final : public SemaBase {
                                   SourceLocation UsingLoc,
                                   SourceLocation EnumLoc, SourceRange TyLoc,
                                   const IdentifierInfo &II, ParsedType Ty,
-                                  CXXScopeSpec *SS = nullptr);
+                                  const CXXScopeSpec &SS);
   Decl *ActOnAliasDeclaration(Scope *CurScope, AccessSpecifier AS,
                               MultiTemplateParamsArg TemplateParams,
                               SourceLocation UsingLoc, UnqualifiedId &Name,

clang/include/clang/StaticAnalyzer/Core/PathSensitive/MemRegion.h

@@ -1548,8 +1548,8 @@ class MemRegionManager {
   ///  a specified FieldDecl.  'superRegion' corresponds to the containing
   ///  memory region (which typically represents the memory representing
   ///  a structure or class).
-  const FieldRegion *getFieldRegion(const FieldDecl *fd,
-                                    const SubRegion* superRegion);
+  const FieldRegion *getFieldRegion(const FieldDecl *FD,
+                                    const SubRegion *SuperRegion);
 
   const FieldRegion *getFieldRegionWithSuper(const FieldRegion *FR,
                                              const SubRegion *superRegion) {

clang/lib/AST/ByteCode/Compiler.cpp

@@ -4199,8 +4199,7 @@ template <class Emitter> bool Compiler<Emitter>::visit(const Expr *E) {
     return this->discard(E);
 
   // Create local variable to hold the return value.
-  if (!E->isGLValue() && !E->getType()->isAnyComplexType() &&
-      !canClassify(E->getType())) {
+  if (!E->isGLValue() && !canClassify(E->getType())) {
     UnsignedOrNone LocalIndex = allocateLocal(E);
     if (!LocalIndex)
       return false;

clang/lib/CIR/CodeGen/CIRGenRecordLayoutBuilder.cpp

@@ -108,6 +108,16 @@ struct CIRRecordLowering final {
   // not the primary vbase of some base class.
   bool hasOwnStorage(const CXXRecordDecl *decl, const CXXRecordDecl *query);
 
+  /// The Microsoft bitfield layout rule allocates discrete storage
+  /// units of the field's formal type and only combines adjacent
+  /// fields of the same formal type.  We want to emit a layout with
+  /// these discrete storage units instead of combining them into a
+  /// continuous run.
+  bool isDiscreteBitFieldABI() {
+    return astContext.getTargetInfo().getCXXABI().isMicrosoft() ||
+           recordDecl->isMsStruct(astContext);
+  }
+
   CharUnits bitsToCharUnits(uint64_t bitOffset) {
     return astContext.toCharUnitsFromBits(bitOffset);
   }
@@ -323,7 +333,45 @@ void CIRRecordLowering::fillOutputFields() {
 RecordDecl::field_iterator
 CIRRecordLowering::accumulateBitFields(RecordDecl::field_iterator field,
                                        RecordDecl::field_iterator fieldEnd) {
-  assert(!cir::MissingFeatures::isDiscreteBitFieldABI());
+  if (isDiscreteBitFieldABI()) {
+    // run stores the first element of the current run of bitfields. fieldEnd is
+    // used as a special value to note that we don't have a current run. A
+    // bitfield run is a contiguous collection of bitfields that can be stored
+    // in the same storage block. Zero-sized bitfields and bitfields that would
+    // cross an alignment boundary break a run and start a new one.
+    RecordDecl::field_iterator run = fieldEnd;
+    // tail is the offset of the first bit off the end of the current run. It's
+    // used to determine if the ASTRecordLayout is treating these two bitfields
+    // as contiguous. StartBitOffset is offset of the beginning of the Run.
+    uint64_t startBitOffset, tail = 0;
+    for (; field != fieldEnd && field->isBitField(); ++field) {
+      // Zero-width bitfields end runs.
+      if (field->isZeroLengthBitField()) {
+        run = fieldEnd;
+        continue;
+      }
+      uint64_t bitOffset = getFieldBitOffset(*field);
+      mlir::Type type = cirGenTypes.convertTypeForMem(field->getType());
+      // If we don't have a run yet, or don't live within the previous run's
+      // allocated storage then we allocate some storage and start a new run.
+      if (run == fieldEnd || bitOffset >= tail) {
+        run = field;
+        startBitOffset = bitOffset;
+        tail = startBitOffset + dataLayout.getTypeAllocSizeInBits(type);
+        // Add the storage member to the record.  This must be added to the
+        // record before the bitfield members so that it gets laid out before
+        // the bitfields it contains get laid out.
+        members.push_back(
+            makeStorageInfo(bitsToCharUnits(startBitOffset), type));
+      }
+      // Bitfields get the offset of their storage but come afterward and remain
+      // there after a stable sort.
+      members.push_back(MemberInfo(bitsToCharUnits(startBitOffset),
+                                   MemberInfo::InfoKind::Field, nullptr,
+                                   *field));
+    }
+    return field;
+  }
 
   CharUnits regSize =
       bitsToCharUnits(astContext.getTargetInfo().getRegisterWidth());

clang/lib/CodeGen/CGHLSLBuiltins.cpp

@@ -342,10 +342,10 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
   }
   case Builtin::BI__builtin_hlsl_resource_handlefromimplicitbinding: {
     llvm::Type *HandleTy = CGM.getTypes().ConvertType(E->getType());
-    Value *SpaceOp = EmitScalarExpr(E->getArg(1));
-    Value *RangeOp = EmitScalarExpr(E->getArg(2));
-    Value *IndexOp = EmitScalarExpr(E->getArg(3));
-    Value *OrderID = EmitScalarExpr(E->getArg(4));
+    Value *OrderID = EmitScalarExpr(E->getArg(1));
+    Value *SpaceOp = EmitScalarExpr(E->getArg(2));
+    Value *RangeOp = EmitScalarExpr(E->getArg(3));
+    Value *IndexOp = EmitScalarExpr(E->getArg(4));
     Value *Name = EmitScalarExpr(E->getArg(5));
     llvm::Intrinsic::ID IntrinsicID =
         CGM.getHLSLRuntime().getCreateHandleFromImplicitBindingIntrinsic();

clang/lib/Headers/avx512fintrin.h

@@ -1463,12 +1463,12 @@ _mm512_mask_mullo_epi32(__m512i __W, __mmask16 __M, __m512i __A, __m512i __B) {
                                              (__v16si)__W);
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512
-_mm512_mullox_epi64 (__m512i __A, __m512i __B) {
+static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
+_mm512_mullox_epi64(__m512i __A, __m512i __B) {
   return (__m512i) ((__v8du) __A * (__v8du) __B);
 }
 
-static __inline__ __m512i __DEFAULT_FN_ATTRS512
+static __inline__ __m512i __DEFAULT_FN_ATTRS512_CONSTEXPR
 _mm512_mask_mullox_epi64(__m512i __W, __mmask8 __U, __m512i __A, __m512i __B) {
   return (__m512i)__builtin_ia32_selectq_512((__mmask8)__U,
                                              (__v8di)_mm512_mullox_epi64(__A, __B),