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[RISCV][NFC] Rename simm12 to simm12_lo (#160380)
This more closely matches what we have done for uimm20, and should allow us to in future differentiate between places that accept %*lo(expr) and those where that is not allowed. I have not introduced a `simm12` node for the moment, so that downstream users notice the change.
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -811,6 +811,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
811811
bool isSImm6() const { return isSImm<6>(); }
812812
bool isSImm10() const { return isSImm<10>(); }
813813
bool isSImm11() const { return isSImm<11>(); }
814+
bool isSImm12() const { return isSImm<12>(); }
814815
bool isSImm16() const { return isSImm<16>(); }
815816
bool isSImm26() const { return isSImm<26>(); }
816817

@@ -859,7 +860,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
859860
return SignExtend64<32>(Imm);
860861
}
861862

862-
bool isSImm12() const {
863+
bool isSImm12LO() const {
863864
if (!isExpr())
864865
return false;
865866

@@ -1599,6 +1600,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
15991600
case Match_InvalidUImm16NonZero:
16001601
return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 16) - 1);
16011602
case Match_InvalidSImm12:
1603+
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 11),
1604+
(1 << 11) - 1);
1605+
case Match_InvalidSImm12LO:
16021606
return generateImmOutOfRangeError(
16031607
Operands, ErrorInfo, -(1 << 11), (1 << 11) - 1,
16041608
"operand must be a symbol with %lo/%pcrel_lo/%tprel_lo specifier or an "

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -41,12 +41,12 @@ def GIImmPlus1 :
4141
def PtrVT : PtrValueTypeByHwMode<XLenVT, 0>;
4242

4343
// Define pattern expansions for pointer ult/slt conditional codes
44-
def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
45-
(SLTIU GPR:$rs1, simm12:$imm12)>;
44+
def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12_lo:$imm12)),
45+
(SLTIU GPR:$rs1, simm12_lo:$imm12)>;
4646
def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
4747
(SLTU GPR:$rs1, GPR:$rs2)>;
48-
def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)),
49-
(SLTI GPR:$rs1, simm12:$imm12)>;
48+
def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12_lo:$imm12)),
49+
(SLTI GPR:$rs1, simm12_lo:$imm12)>;
5050
def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
5151
(SLT GPR:$rs1, GPR:$rs2)>;
5252

@@ -72,12 +72,12 @@ def : Pat<(XLenVT (setgt (Ty GPR:$rs1), (Ty simm12Minus1Nonzero:$imm))),
7272
(XORI (SLTI GPR:$rs1, (ImmPlus1 simm12Minus1Nonzero:$imm)), 1)>;
7373
def : Pat<(XLenVT (setgt (Ty GPR:$rs1), (Ty GPR:$rs2))),
7474
(SLT GPR:$rs2, GPR:$rs1)>;
75-
def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), (Ty simm12:$imm))),
76-
(XORI (SLTIU GPR:$rs1, simm12:$imm), 1)>;
75+
def : Pat<(XLenVT (setuge (XLenVT GPR:$rs1), (Ty simm12_lo:$imm))),
76+
(XORI (SLTIU GPR:$rs1, simm12_lo:$imm), 1)>;
7777
def : Pat<(XLenVT (setuge (Ty GPR:$rs1), (Ty GPR:$rs2))),
7878
(XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
79-
def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty simm12:$imm))),
80-
(XORI (SLTI GPR:$rs1, simm12:$imm), 1)>;
79+
def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty simm12_lo:$imm))),
80+
(XORI (SLTI GPR:$rs1, simm12_lo:$imm), 1)>;
8181
def : Pat<(XLenVT (setge (Ty GPR:$rs1), (Ty GPR:$rs2))),
8282
(XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
8383
def : Pat<(XLenVT (setule (Ty GPR:$rs1), (Ty simm12Minus1NonzeroNonNeg1:$imm))),
@@ -143,8 +143,8 @@ def : Pat<(anyext (i32 GPR:$src)), (COPY GPR:$src)>;
143143
def : Pat<(sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
144144
def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
145145

146-
def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12:$imm)), i32),
147-
(ADDIW GPR:$rs1, simm12:$imm)>;
146+
def : Pat<(sext_inreg (i64 (add GPR:$rs1, simm12_lo:$imm)), i32),
147+
(ADDIW GPR:$rs1, simm12_lo:$imm)>;
148148

149149
// Use sext if the sign bit of the input is 0.
150150
def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

Lines changed: 52 additions & 50 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -529,11 +529,11 @@ def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>;
529529

530530
/// Loads
531531
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
532-
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
532+
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12_lo:$imm12), []>;
533533

534534
/// Stores
535535
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
536-
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
536+
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12_lo:$imm12), []>;
537537
} // Predicates = [HasStdExtZdinx, IsRV32]
538538

539539
let Predicates = [HasStdExtZdinx, HasStdExtZilsd, IsRV32] in {

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -196,15 +196,15 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
196196
class FPLoad_r<bits<3> funct3, string opcodestr, DAGOperand rty,
197197
SchedWrite sw>
198198
: RVInstI<funct3, OPC_LOAD_FP, (outs rty:$rd),
199-
(ins GPRMem:$rs1, simm12:$imm12),
199+
(ins GPRMem:$rs1, simm12_lo:$imm12),
200200
opcodestr, "$rd, ${imm12}(${rs1})">,
201201
Sched<[sw, ReadFMemBase]>;
202202

203203
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
204204
class FPStore_r<bits<3> funct3, string opcodestr, DAGOperand rty,
205205
SchedWrite sw>
206206
: RVInstS<funct3, OPC_STORE_FP, (outs),
207-
(ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
207+
(ins rty:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
208208
opcodestr, "$rs2, ${imm12}(${rs1})">,
209209
Sched<[sw, ReadFStoreData, ReadFMemBase]>;
210210

‎llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ class SFBALU_rr
6060
class SFBALU_ri
6161
: Pseudo<(outs GPR:$dst),
6262
(ins GPR:$lhs, GPR:$rhs, cond_code:$cc, GPR:$falsev, GPR:$rs1,
63-
simm12:$imm), []>,
63+
simm12_lo:$imm), []>,
6464
Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]> {
6565
let hasSideEffects = 0;
6666
let mayLoad = 0;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -271,7 +271,7 @@ class CVInstImmBranch<bits<3> funct3, dag outs, dag ins,
271271
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
272272
class CVLoad_ri_inc<bits<3> funct3, string opcodestr>
273273
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
274-
(ins GPRMem:$rs1, simm12:$imm12),
274+
(ins GPRMem:$rs1, simm12_lo:$imm12),
275275
opcodestr, "$rd, (${rs1}), ${imm12}"> {
276276
let Constraints = "$rs1_wb = $rs1";
277277
}
@@ -292,7 +292,7 @@ class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
292292
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
293293
class CVStore_ri_inc<bits<3> funct3, string opcodestr>
294294
: RVInstS<funct3, OPC_CUSTOM_1, (outs GPR:$rs1_wb),
295-
(ins GPR:$rs2, GPR:$rs1, simm12:$imm12),
295+
(ins GPR:$rs2, GPR:$rs1, simm12_lo:$imm12),
296296
opcodestr, "$rs2, (${rs1}), ${imm12}"> {
297297
let Constraints = "$rs1_wb = $rs1";
298298
}
@@ -332,7 +332,7 @@ class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
332332

333333
class CVLoad_ri<bits<3> funct3, string opcodestr>
334334
: RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
335-
(ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
335+
(ins GPRMem:$rs1, simm12_lo:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
336336

337337
//===----------------------------------------------------------------------===//
338338
// Instructions
@@ -673,8 +673,8 @@ class CVLdrrPat<PatFrag LoadOp, RVInst Inst>
673673
(Inst CVrr:$regreg)>;
674674

675675
class CVStriPat<PatFrag StoreOp, RVInst Inst>
676-
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12:$imm12),
677-
(Inst GPR:$rs2, GPR:$rs1, simm12:$imm12)>;
676+
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, simm12_lo:$imm12),
677+
(Inst GPR:$rs2, GPR:$rs1, simm12_lo:$imm12)>;
678678

679679
class CVStrriPat<PatFrag StoreOp, RVInst Inst>
680680
: Pat<(StoreOp (XLenVT GPR:$rs2), GPR:$rs1, GPR:$rs3),

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -953,7 +953,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
953953
}
954954

955955
def QC_MULIADD : RVInstI<0b110, OPC_CUSTOM_0, (outs GPRNoX0:$rd_wb),
956-
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12),
956+
(ins GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12),
957957
"qc.muliadd", "$rd, $rs1, $imm12"> {
958958
let Constraints = "$rd = $rd_wb";
959959
}
@@ -1411,8 +1411,8 @@ class SelectQCbi<CondCode Cond, DAGOperand InTyImm, Pseudo OpNode >
14111411
(IntCCtoRISCVCC $cc), GPRNoX0:$truev, GPRNoX0:$falsev)>;
14121412

14131413
let Predicates = [HasVendorXqciac, IsRV32] in {
1414-
def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))),
1415-
(QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>;
1414+
def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12_lo:$imm12))),
1415+
(QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12_lo:$imm12)>;
14161416
def : Pat<(i32 (add_like_non_imm12 (shl GPRNoX0:$rs1, uimm5gt3:$imm), GPRNoX0:$rs2)),
14171417
(QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>;
14181418
def : Pat<(i32 (riscv_shl_add GPRNoX0:$rs1, uimm5gt3:$imm, GPRNoX0:$rs2)),
@@ -1667,27 +1667,27 @@ def : CompressPat<(QC_E_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm),
16671667
(C_LW GPRC:$rd, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
16681668
def : CompressPat<(QC_E_LW GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm),
16691669
(C_LWSP GPRNoX0:$rd, SPMem:$rs1, uimm8_lsb00:$imm)>;
1670-
def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12:$imm12),
1671-
(LB GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
1672-
def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12),
1673-
(LBU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
1674-
def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12:$imm12),
1675-
(LH GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
1676-
def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12),
1677-
(LHU GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
1678-
def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12:$imm12),
1679-
(LW GPR:$rd, GPRMem:$rs1, simm12:$imm12)>;
1670+
def : CompressPat<(QC_E_LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
1671+
(LB GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
1672+
def : CompressPat<(QC_E_LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
1673+
(LBU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
1674+
def : CompressPat<(QC_E_LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
1675+
(LH GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
1676+
def : CompressPat<(QC_E_LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
1677+
(LHU GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
1678+
def : CompressPat<(QC_E_LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12),
1679+
(LW GPR:$rd, GPRMem:$rs1, simm12_lo:$imm12)>;
16801680

16811681
def : CompressPat<(QC_E_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm),
16821682
(C_SW GPRC:$rs2, GPRCMem:$rs1, uimm7_lsb00:$imm)>;
16831683
def : CompressPat<(QC_E_SW GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm),
16841684
(C_SWSP GPR:$rs2, SPMem:$rs1, uimm8_lsb00:$imm)>;
1685-
def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
1686-
(SB GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
1687-
def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
1688-
(SH GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
1689-
def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12),
1690-
(SW GPR:$rs2, GPRMem:$rs1, simm12:$imm12)>;
1685+
def : CompressPat<(QC_E_SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
1686+
(SB GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
1687+
def : CompressPat<(QC_E_SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
1688+
(SH GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
1689+
def : CompressPat<(QC_E_SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12),
1690+
(SW GPR:$rs2, GPRMem:$rs1, simm12_lo:$imm12)>;
16911691
} // isCompressOnly = true, Predicates = [HasVendorXqcilo, IsRV32]
16921692

16931693
let Predicates = [HasVendorXqcicm, IsRV32] in {
@@ -1752,23 +1752,23 @@ def : CompressPat<(QC_E_ADDAI X2, simm10_lsb0000nonzero:$imm),
17521752
def : CompressPat<(QC_E_ADDI X2, X2, simm10_lsb0000nonzero:$imm),
17531753
(C_ADDI16SP X2, simm10_lsb0000nonzero:$imm)>;
17541754

1755-
def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
1756-
(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
1757-
def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
1758-
(ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
1759-
def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
1760-
(ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
1761-
def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm),
1762-
(XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12:$imm)>;
1763-
1764-
def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12:$imm),
1765-
(ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
1766-
def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12:$imm),
1767-
(ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
1768-
def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12:$imm),
1769-
(ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
1770-
def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12:$imm),
1771-
(XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
1755+
def : CompressPat<(QC_E_ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
1756+
(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;
1757+
def : CompressPat<(QC_E_ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
1758+
(ANDI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;
1759+
def : CompressPat<(QC_E_ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
1760+
(ORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;
1761+
def : CompressPat<(QC_E_XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm),
1762+
(XORI GPRNoX0:$rs1, GPRNoX0:$rs2, simm12_lo:$imm)>;
1763+
1764+
def : CompressPat<(QC_E_ADDAI GPRNoX0:$rd, simm12_lo:$imm),
1765+
(ADDI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
1766+
def : CompressPat<(QC_E_ANDAI GPRNoX0:$rd, simm12_lo:$imm),
1767+
(ANDI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
1768+
def : CompressPat<(QC_E_ORAI GPRNoX0:$rd, simm12_lo:$imm),
1769+
(ORI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
1770+
def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12_lo:$imm),
1771+
(XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12_lo:$imm)>;
17721772
} // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]
17731773

17741774
let isCompressOnly = true, Predicates = [HasVendorXqciac, IsRV32] in {

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