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AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints
This removes special case processing in TargetInstrInfo::getRegClass to fixup register operands which depending on the subtarget support AGPRs, or require even aligned registers. This regresses assembler diagnostics, which currently work by hackily accepting invalid cases and then post-rejecting a validly parsed instruction. On the plus side this now emits a comment when disassembling unaligned registers for targets with the alignment requirement.
1 parent a38794f commit 5b4d86d

31 files changed

+2770
-2606
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2752,6 +2752,9 @@ def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
27522752
def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
27532753
AssemblerPredicate<(all_of FeatureMAIInsts)>;
27542754

2755+
def NotHasMAIInsts : Predicate<"!Subtarget->hasMAIInsts()">,
2756+
AssemblerPredicate<(all_of (not FeatureMAIInsts))>;
2757+
27552758
def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
27562759
AssemblerPredicate<(all_of FeatureSMemRealTime)>;
27572760

@@ -2926,6 +2929,20 @@ def HasLdsBarrierArriveAtomic : Predicate<"Subtarget->hasLdsBarrierArriveAtomic(
29262929
def HasSetPrioIncWgInst : Predicate<"Subtarget->hasSetPrioIncWgInst()">,
29272930
AssemblerPredicate<(all_of FeatureSetPrioIncWgInst)>;
29282931

2932+
def NeedsAlignedVGPRs : Predicate<"Subtarget->needsAlignedVGPRs()">,
2933+
AssemblerPredicate<(all_of FeatureRequiresAlignedVGPRs)>;
2934+
2935+
//===----------------------------------------------------------------------===//
2936+
// HwModes
2937+
//===----------------------------------------------------------------------===//
2938+
2939+
// gfx90a-gfx950. Has AGPRs, and also the align2 VGPR/AGPR requirement
2940+
def AVAlign2LoadStoreMode : HwMode<[HasMAIInsts, NeedsAlignedVGPRs]>;
2941+
2942+
// gfx1250, has alignment requirement but no AGPRs.
2943+
def AlignedVGPRNoAGPRMode : HwMode<[NotHasMAIInsts, NeedsAlignedVGPRs]>;
2944+
2945+
29292946
// Include AMDGPU TD files
29302947
include "SISchedule.td"
29312948
include "GCNProcessors.td"

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -393,12 +393,13 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
393393

394394
switch (N->getMachineOpcode()) {
395395
default: {
396-
const MCInstrDesc &Desc =
397-
Subtarget->getInstrInfo()->get(N->getMachineOpcode());
396+
const SIInstrInfo *TII = Subtarget->getInstrInfo();
397+
const MCInstrDesc &Desc = TII->get(N->getMachineOpcode());
398398
unsigned OpIdx = Desc.getNumDefs() + OpNo;
399399
if (OpIdx >= Desc.getNumOperands())
400400
return nullptr;
401-
int RegClass = Desc.operands()[OpIdx].RegClass;
401+
402+
int16_t RegClass = TII->getOpRegClassID(Desc.operands()[OpIdx]);
402403
if (RegClass == -1)
403404
return nullptr;
404405

@@ -4338,7 +4339,8 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
43384339
if (!RC || SIRI->isSGPRClass(RC))
43394340
return false;
43404341

4341-
if (RC != &AMDGPU::VS_32RegClass && RC != &AMDGPU::VS_64RegClass) {
4342+
if (RC != &AMDGPU::VS_32RegClass && RC != &AMDGPU::VS_64RegClass &&
4343+
RC != &AMDGPU::VS_64_Align2RegClass) {
43424344
AllUsesAcceptSReg = false;
43434345
SDNode *User = U->getUser();
43444346
if (User->isMachineOpcode()) {
@@ -4352,7 +4354,8 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
43524354
const TargetRegisterClass *CommutedRC =
43534355
getOperandRegClass(U->getUser(), CommutedOpNo);
43544356
if (CommutedRC == &AMDGPU::VS_32RegClass ||
4355-
CommutedRC == &AMDGPU::VS_64RegClass)
4357+
CommutedRC == &AMDGPU::VS_64RegClass ||
4358+
CommutedRC == &AMDGPU::VS_64_Align2RegClass)
43564359
AllUsesAcceptSReg = true;
43574360
}
43584361
}

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,6 +1342,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
13421342
bool ForcedDPP = false;
13431343
bool ForcedSDWA = false;
13441344
KernelScopeInfo KernelScope;
1345+
const unsigned HwMode;
13451346

13461347
/// @name Auto-generated Match Functions
13471348
/// {
@@ -1351,6 +1352,13 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
13511352

13521353
/// }
13531354

1355+
/// Get size of register operand
1356+
unsigned getRegOperandSize(const MCInstrDesc &Desc, unsigned OpNo) const {
1357+
assert(OpNo < Desc.NumOperands);
1358+
int16_t RCID = MII.getOpRegClassID(Desc.operands()[OpNo], HwMode);
1359+
return getRegBitWidth(RCID) / 8;
1360+
}
1361+
13541362
private:
13551363
void createConstantSymbol(StringRef Id, int64_t Val);
13561364

@@ -1437,9 +1445,9 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
14371445
using OptionalImmIndexMap = std::map<AMDGPUOperand::ImmTy, unsigned>;
14381446

14391447
AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
1440-
const MCInstrInfo &MII,
1441-
const MCTargetOptions &Options)
1442-
: MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {
1448+
const MCInstrInfo &MII, const MCTargetOptions &Options)
1449+
: MCTargetAsmParser(Options, STI, MII), Parser(_Parser),
1450+
HwMode(STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
14431451
MCAsmParserExtension::Initialize(Parser);
14441452

14451453
setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));
@@ -4057,7 +4065,7 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
40574065
if ((DMaskIdx == -1 || TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray
40584066
return true;
40594067

4060-
unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);
4068+
unsigned VDataSize = getRegOperandSize(Desc, VDataIdx);
40614069
unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;
40624070
unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;
40634071
if (DMask == 0)
@@ -4122,8 +4130,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
41224130
const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
41234131
bool IsNSA = SrsrcIdx - VAddr0Idx > 1;
41244132
unsigned ActualAddrSize =
4125-
IsNSA ? SrsrcIdx - VAddr0Idx
4126-
: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;
4133+
IsNSA ? SrsrcIdx - VAddr0Idx : getRegOperandSize(Desc, VAddr0Idx) / 4;
41274134

41284135
unsigned ExpectedAddrSize =
41294136
AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());
@@ -4133,8 +4140,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
41334140
ExpectedAddrSize >
41344141
getNSAMaxSize(Desc.TSFlags & SIInstrFlags::VSAMPLE)) {
41354142
int VAddrLastIdx = SrsrcIdx - 1;
4136-
unsigned VAddrLastSize =
4137-
AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4;
4143+
unsigned VAddrLastSize = getRegOperandSize(Desc, VAddrLastIdx) / 4;
41384144

41394145
ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;
41404146
}
@@ -4380,7 +4386,8 @@ bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
43804386
return true;
43814387

43824388
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
4383-
if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)
4389+
if (TRI->getRegClass(MII.getOpRegClassID(Desc.operands()[0], HwMode))
4390+
.getSizeInBits() <= 128)
43844391
return true;
43854392

43864393
if (TRI->regsOverlap(Src2Reg, DstReg)) {
@@ -4941,7 +4948,7 @@ bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
49414948
unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();
49424949

49434950
if (!AMDGPU::isLegalDPALU_DPPControl(getSTI(), DppCtrl) &&
4944-
AMDGPU::isDPALU_DPP(MII.get(Opc), getSTI())) {
4951+
AMDGPU::isDPALU_DPP(MII.get(Opc), MII, getSTI())) {
49454952
// DP ALU DPP is supported for row_newbcast only on GFX9* and row_share
49464953
// only on GFX12.
49474954
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);
@@ -5459,7 +5466,8 @@ bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst,
54595466
unsigned Fmt = Inst.getOperand(FmtIdx).getImm();
54605467
int SrcIdx = AMDGPU::getNamedOperandIdx(Opc, SrcOp);
54615468
unsigned RegSize =
5462-
TRI->getRegClass(Desc.operands()[SrcIdx].RegClass).getSizeInBits();
5469+
TRI->getRegClass(MII.getOpRegClassID(Desc.operands()[SrcIdx], HwMode))
5470+
.getSizeInBits();
54635471

54645472
if (RegSize == AMDGPU::wmmaScaleF8F6F4FormatToNumRegs(Fmt) * 32)
54655473
return true;

‎llvm/lib/Target/AMDGPU/BUFInstructions.td‎

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -417,10 +417,10 @@ class getBUFVDataRegisterOperandForOp<RegisterOperand Op, bit isTFE> {
417417
}
418418

419419
class getMUBUFInsDA<list<RegisterOperand> vdataList,
420-
list<RegisterClass> vaddrList, bit isTFE, bit hasRestrictedSOffset> {
420+
list<RegisterClassLike> vaddrList, bit isTFE, bit hasRestrictedSOffset> {
421421
RegisterOperand vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
422-
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
423-
RegisterOperand vdata_op = getBUFVDataRegisterOperandForOp<vdataClass, isTFE>.ret;
422+
RegisterClassLike vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
423+
RegisterOperand vdata_op = getBUFVDataRegisterOperand<!cast<SIRegisterClassLike>(vdataClass.RegClass).Size, isTFE>.ret;
424424

425425
dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
426426
dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
@@ -453,8 +453,8 @@ class getMUBUFIns<int addrKind, list<RegisterOperand> vdataList, bit isTFE, bit
453453
!if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList, [], isTFE, hasRestrictedSOffset>.ret,
454454
!if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPR_32], isTFE, hasRestrictedSOffset>.ret,
455455
!if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPR_32], isTFE, hasRestrictedSOffset>.ret,
456-
!if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64], isTFE, hasRestrictedSOffset>.ret,
457-
!if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64], isTFE, hasRestrictedSOffset>.ret,
456+
!if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64_AlignTarget], isTFE, hasRestrictedSOffset>.ret,
457+
!if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64_AlignTarget], isTFE, hasRestrictedSOffset>.ret,
458458
(ins))))));
459459
}
460460

@@ -677,8 +677,8 @@ class MUBUF_Pseudo_Store_Lds<string opName>
677677
}
678678

679679
class getMUBUFAtomicInsDA<RegisterOperand vdata_op, bit vdata_in, bit hasRestrictedSOffset,
680-
list<RegisterClass> vaddrList=[]> {
681-
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
680+
list<RegisterClassLike> vaddrList=[]> {
681+
RegisterClassLike vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
682682

683683
dag VData = !if(vdata_in, (ins vdata_op:$vdata_in), (ins vdata_op:$vdata));
684684
dag Data = !if(!empty(vaddrList), VData, !con(VData, (ins vaddrClass:$vaddr)));
@@ -702,9 +702,9 @@ class getMUBUFAtomicIns<int addrKind,
702702
!if(!eq(addrKind, BUFAddrKind.IdxEn),
703703
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VGPR_32]>.ret,
704704
!if(!eq(addrKind, BUFAddrKind.BothEn),
705-
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64]>.ret,
705+
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64_AlignTarget]>.ret,
706706
!if(!eq(addrKind, BUFAddrKind.Addr64),
707-
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64]>.ret,
707+
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64_AlignTarget]>.ret,
708708
(ins))))));
709709
}
710710

@@ -1568,11 +1568,12 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
15681568
# !if(!eq(RtnMode, "ret"), "", "_noret")
15691569
# "_" # vt);
15701570
defvar InstSuffix = !if(!eq(RtnMode, "ret"), "_RTN", "");
1571-
defvar data_vt_RC = getVregSrcForVT<data_vt>.ret.RegClass;
1571+
defvar data_op = getVregSrcForVT<data_vt>.ret;
1572+
defvar data_vt_RC = getVregClassForVT<data_vt>.ret;
15721573

15731574
let AddedComplexity = !if(!eq(RtnMode, "ret"), 0, 1) in {
15741575
defvar OffsetResDag = (!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix)
1575-
data_vt_RC:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
1576+
data_op:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
15761577
Offset:$offset);
15771578
def : GCNPat<
15781579
(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), data_vt:$vdata_in)),
@@ -1583,7 +1584,7 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
15831584
>;
15841585

15851586
defvar Addr64ResDag = (!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix)
1586-
data_vt_RC:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
1587+
data_op:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
15871588
SCSrc_b32:$soffset, Offset:$offset);
15881589
def : GCNPat<
15891590
(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
@@ -1832,7 +1833,7 @@ multiclass SIBufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, stri
18321833
(extract_cpol_set_glc $auxiliary),
18331834
(extract_cpol $auxiliary));
18341835
defvar SrcRC = getVregSrcForVT<vt>.ret;
1835-
defvar DataRC = getVregSrcForVT<data_vt>.ret.RegClass;
1836+
defvar DataRC = getVregClassForVT<data_vt>.ret;
18361837
defvar SubLo = !if(!eq(vt, i32), sub0, sub0_sub1);
18371838
defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3);
18381839

@@ -2088,7 +2089,7 @@ defm : MUBUFStore_PatternOffset <"BUFFER_STORE_SHORT", i16, store_global>;
20882089

20892090
multiclass MUBUFScratchStorePat_Common <string Instr,
20902091
ValueType vt, PatFrag st,
2091-
RegisterClass rc = VGPR_32> {
2092+
RegisterClassLike rc = VGPR_32> {
20922093
def : GCNPat <
20932094
(st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
20942095
i32:$soffset, i32:$offset)),
@@ -2104,7 +2105,7 @@ multiclass MUBUFScratchStorePat_Common <string Instr,
21042105

21052106
multiclass MUBUFScratchStorePat <string Instr,
21062107
ValueType vt, PatFrag st,
2107-
RegisterClass rc = VGPR_32> {
2108+
RegisterClassLike rc = VGPR_32> {
21082109
let SubtargetPredicate = HasUnrestrictedSOffset in {
21092110
defm : MUBUFScratchStorePat_Common<Instr, vt, st, rc>;
21102111
}

‎llvm/lib/Target/AMDGPU/DSInstructions.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -904,7 +904,7 @@ let SubtargetPredicate = isGFX1250Plus in {
904904
let WaveSizePredicate = isWave32, mayStore = 0 in {
905905
let OtherPredicates = [HasTransposeLoadF4F6Insts] in {
906906
defm DS_LOAD_TR4_B64 : DS_1A_RET_NoM0<"ds_load_tr4_b64", VGPROp_64>;
907-
defm DS_LOAD_TR6_B96 : DS_1A_RET_NoM0<"ds_load_tr6_b96", VGPROp_96>;
907+
defm DS_LOAD_TR6_B96 : DS_1A_RET_NoM0<"ds_load_tr6_b96", VGPROp_96_Align1>;
908908
} // End OtherPredicates = [HasTransposeLoadF4F6Insts]
909909
defm DS_LOAD_TR8_B64 : DS_1A_RET_NoM0<"ds_load_tr8_b64", VGPROp_64>;
910910
defm DS_LOAD_TR16_B128 : DS_1A_RET_NoM0<"ds_load_tr16_b128", VGPROp_128>;
@@ -934,7 +934,7 @@ let WaveSizePredicate = isWave64, SubtargetPredicate = HasGFX950Insts, mayStore
934934
defm DS_READ_B64_TR_B4 : DS_1A_RET_NoM0<"ds_read_b64_tr_b4", AVLdSt_64>;
935935
defm DS_READ_B64_TR_B8 : DS_1A_RET_NoM0<"ds_read_b64_tr_b8", AVLdSt_64>;
936936
defm DS_READ_B64_TR_B16 : DS_1A_RET_NoM0<"ds_read_b64_tr_b16", AVLdSt_64>;
937-
defm DS_READ_B96_TR_B6 : DS_1A_RET_NoM0<"ds_read_b96_tr_b6", AVLdSt_96>;
937+
defm DS_READ_B96_TR_B6 : DS_1A_RET_NoM0<"ds_read_b96_tr_b6", AVLdSt_96_Align1>;
938938
}
939939

940940
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,9 @@ static int64_t getInlineImmVal64(unsigned Imm);
5656
AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
5757
MCContext &Ctx, MCInstrInfo const *MCII)
5858
: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
59-
MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
59+
MAI(*Ctx.getAsmInfo()),
60+
HwModeRegClass(STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)),
61+
TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
6062
CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
6163
// ToDo: AMDGPUDisassembler supports only VI ISA.
6264
if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
@@ -824,7 +826,8 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
824826
}
825827
}
826828

827-
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) {
829+
const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
830+
if (Desc.TSFlags & SIInstrFlags::MIMG) {
828831
int VAddr0Idx =
829832
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
830833
int RsrcIdx =
@@ -837,7 +840,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
837840
for (unsigned i = 0; i < NSAArgs; ++i) {
838841
const unsigned VAddrIdx = VAddr0Idx + 1 + i;
839842
auto VAddrRCID =
840-
MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass;
843+
MCII->getOpRegClassID(Desc.operands()[VAddrIdx], HwModeRegClass);
841844
MI.insert(MI.begin() + VAddrIdx, createRegOperand(VAddrRCID, Bytes[i]));
842845
}
843846
Bytes = Bytes.slice(4 * NSAWords);
@@ -1310,7 +1313,8 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
13101313
// Widen the register to the correct number of enabled channels.
13111314
MCRegister NewVdata;
13121315
if (DstSize != Info->VDataDwords) {
1313-
auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
1316+
auto DataRCID = MCII->getOpRegClassID(
1317+
MCII->get(NewOpcode).operands()[VDataIdx], HwModeRegClass);
13141318

13151319
// Get first subregister of VData
13161320
MCRegister Vdata0 = MI.getOperand(VDataIdx).getReg();
@@ -1337,7 +1341,9 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
13371341
MCRegister VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
13381342
VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
13391343

1340-
auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;
1344+
auto AddrRCID = MCII->getOpRegClassID(
1345+
MCII->get(NewOpcode).operands()[VAddrSAIdx], HwModeRegClass);
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const MCRegisterClass &NewRC = MRI.getRegClass(AddrRCID);
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NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, &NewRC);
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NewVAddrSA = CheckVGPROverflow(NewVAddrSA, NewRC, MRI);

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ class AMDGPUDisassembler : public MCDisassembler {
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std::unique_ptr<MCInstrInfo const> const MCII;
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const MCRegisterInfo &MRI;
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const MCAsmInfo &MAI;
44+
const unsigned HwModeRegClass;
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const unsigned TargetMaxInstBytes;
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mutable ArrayRef<uint8_t> Bytes;
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mutable uint32_t Literal;

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