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[RISCV] Reduce constant pool usage without FP extension
The recognition range can be extended later.
1 parent acd0899 commit 5b538f8

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8 files changed

+135
-151
lines changed

8 files changed

+135
-151
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp‎

Lines changed: 13 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -745,10 +745,19 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
745745
if (!materializeImm(GPRReg, Imm.getSExtValue(), MIB))
746746
return false;
747747

748-
unsigned Opcode = Size == 64 ? RISCV::FMV_D_X
749-
: Size == 32 ? RISCV::FMV_W_X
750-
: RISCV::FMV_H_X;
751-
auto FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg});
748+
unsigned Opcode = RISCV::INIT_UNDEF;
749+
MachineInstrBuilder FMV;
750+
if (Subtarget->hasStdExtF() || Subtarget->hasStdExtD() ||
751+
Subtarget->hasStdExtZfh()) {
752+
Opcode = Size == 64 ? RISCV::FMV_D_X
753+
: Size == 32 ? RISCV::FMV_W_X
754+
: RISCV::FMV_H_X;
755+
FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg});
756+
} else {
757+
Opcode =
758+
(Subtarget->is64Bit() && Size == 32) ? RISCV::ADDW : RISCV::ADD;
759+
FMV = MIB.buildInstr(Opcode, {DstReg}, {GPRReg, Register(RISCV::X0)});
760+
}
752761
if (!FMV.constrainAllUses(TII, TRI, RBI))
753762
return false;
754763
} else {

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -572,7 +572,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
572572
.legalFor(ST.hasStdExtF(), {s32})
573573
.legalFor(ST.hasStdExtD(), {s64})
574574
.legalFor(ST.hasStdExtZfh(), {s16})
575-
.lowerFor({s32, s64, s128});
575+
.customFor(!ST.is64Bit(), {s32})
576+
.customFor(ST.is64Bit(), {s32, s64})
577+
.lowerFor({s64, s128});
576578

577579
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
578580
.legalFor(ST.hasStdExtF(), {{sXLen, s32}})
@@ -869,6 +871,12 @@ bool RISCVLegalizerInfo::shouldBeInConstantPool(const APInt &APImm,
869871
return !(!SeqLo.empty() && (SeqLo.size() + 2) <= STI.getMaxBuildIntsCost());
870872
}
871873

874+
bool RISCVLegalizerInfo::shouldBeInFConstantPool(const APFloat &APImm) const {
875+
if (APImm.isZero() || APImm.isExactlyValue(1.0))
876+
return false;
877+
return true;
878+
}
879+
872880
bool RISCVLegalizerInfo::legalizeVScale(MachineInstr &MI,
873881
MachineIRBuilder &MIB) const {
874882
const LLT XLenTy(STI.getXLenVT());
@@ -1358,7 +1366,12 @@ bool RISCVLegalizerInfo::legalizeCustom(
13581366
return false;
13591367
case TargetOpcode::G_ABS:
13601368
return Helper.lowerAbsToMaxNeg(MI);
1361-
// TODO: G_FCONSTANT
1369+
case TargetOpcode::G_FCONSTANT: {
1370+
const ConstantFP *ConstVal = MI.getOperand(1).getFPImm();
1371+
if (!shouldBeInFConstantPool(ConstVal->getValue()))
1372+
return true;
1373+
return Helper.lowerFConstant(MI);
1374+
}
13621375
case TargetOpcode::G_CONSTANT: {
13631376
const Function &F = MF.getFunction();
13641377
// TODO: if PSI and BFI are present, add " ||

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ class RISCVLegalizerInfo : public LegalizerInfo {
3939

4040
private:
4141
bool shouldBeInConstantPool(const APInt &APImm, bool ShouldOptForSize) const;
42+
bool shouldBeInFConstantPool(const APFloat &APImm) const;
4243
bool legalizeShlAshrLshr(MachineInstr &MI, MachineIRBuilder &MIRBuilder,
4344
GISelChangeObserver &Observer) const;
4445

‎llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp‎

Lines changed: 19 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,8 @@ using namespace llvm;
112112
RISCVRegisterBankInfo::RISCVRegisterBankInfo(unsigned HwMode)
113113
: RISCVGenRegisterBankInfo(HwMode) {}
114114

115-
static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
115+
static const RegisterBankInfo::ValueMapping *
116+
getFPValueMapping(unsigned Size, bool HasFPExt = true) {
116117
unsigned Idx;
117118
switch (Size) {
118119
default:
@@ -121,10 +122,10 @@ static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
121122
Idx = RISCV::FPRB16Idx;
122123
break;
123124
case 32:
124-
Idx = RISCV::FPRB32Idx;
125+
Idx = HasFPExt ? RISCV::FPRB32Idx : RISCV::GPRB32Idx;
125126
break;
126127
case 64:
127-
Idx = RISCV::FPRB64Idx;
128+
Idx = HasFPExt ? RISCV::FPRB64Idx : RISCV::GPRB64Idx;
128129
break;
129130
}
130131
return &RISCV::ValueMappings[Idx];
@@ -219,6 +220,10 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
219220
const TargetSubtargetInfo &STI = MF.getSubtarget();
220221
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
221222

223+
bool HasFPExt = STI.hasFeature(RISCV::FeatureStdExtF) ||
224+
STI.hasFeature(RISCV::FeatureStdExtD) ||
225+
STI.hasFeature(RISCV::FeatureStdExtZfh);
226+
222227
unsigned GPRSize = getMaximumSize(RISCV::GPRBRegBankID);
223228
assert((GPRSize == 32 || GPRSize == 64) && "Unexpected GPR size");
224229

@@ -266,7 +271,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
266271
if (Ty.isVector())
267272
Mapping = getVRBValueMapping(Size.getKnownMinValue());
268273
else if (isPreISelGenericFloatingPointOpcode(Opc))
269-
Mapping = getFPValueMapping(Size.getFixedValue());
274+
Mapping = getFPValueMapping(Size.getFixedValue(), HasFPExt);
270275
else
271276
Mapping = GPRValueMapping;
272277

@@ -301,7 +306,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
301306
if (DstTy.isVector())
302307
Mapping = getVRBValueMapping(DstMinSize);
303308
else if (anyUseOnlyUseFP(Dst, MRI, TRI))
304-
Mapping = getFPValueMapping(DstMinSize);
309+
Mapping = getFPValueMapping(DstMinSize, HasFPExt);
305310

306311
return getInstructionMapping(DefaultMappingID, /*Cost=*/1, Mapping,
307312
NumOperands);
@@ -339,7 +344,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
339344
// assume this was a floating point load in the IR. If it was
340345
// not, we would have had a bitcast before reaching that
341346
// instruction.
342-
OpdsMapping[0] = getFPValueMapping(Size);
347+
OpdsMapping[0] = getFPValueMapping(Size, HasFPExt);
343348
break;
344349
}
345350

@@ -367,7 +372,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
367372

368373
MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg());
369374
if (onlyDefinesFP(*DefMI, MRI, TRI))
370-
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
375+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
371376
break;
372377
}
373378
case TargetOpcode::G_SELECT: {
@@ -432,7 +437,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
432437

433438
const ValueMapping *Mapping = GPRValueMapping;
434439
if (NumFP >= 2)
435-
Mapping = getFPValueMapping(Ty.getSizeInBits());
440+
Mapping = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
436441

437442
OpdsMapping[0] = OpdsMapping[2] = OpdsMapping[3] = Mapping;
438443
break;
@@ -444,13 +449,13 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
444449
case RISCV::G_FCLASS: {
445450
LLT Ty = MRI.getType(MI.getOperand(1).getReg());
446451
OpdsMapping[0] = GPRValueMapping;
447-
OpdsMapping[1] = getFPValueMapping(Ty.getSizeInBits());
452+
OpdsMapping[1] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
448453
break;
449454
}
450455
case TargetOpcode::G_SITOFP:
451456
case TargetOpcode::G_UITOFP: {
452457
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
453-
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
458+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
454459
OpdsMapping[1] = GPRValueMapping;
455460
break;
456461
}
@@ -468,7 +473,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
468473
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
469474
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
470475
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
471-
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
476+
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
472477
OpdsMapping[1] = GPRValueMapping;
473478
OpdsMapping[2] = GPRValueMapping;
474479
}
@@ -481,7 +486,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
481486
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
482487
OpdsMapping[0] = GPRValueMapping;
483488
OpdsMapping[1] = GPRValueMapping;
484-
OpdsMapping[2] = getFPValueMapping(Ty.getSizeInBits());
489+
OpdsMapping[2] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
485490
}
486491
break;
487492
}
@@ -495,7 +500,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
495500
if ((GPRSize == 32 && ScalarTy.getSizeInBits() == 64) ||
496501
onlyDefinesFP(*DefMI, MRI, TRI)) {
497502
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
498-
OpdsMapping[1] = getFPValueMapping(ScalarTy.getSizeInBits());
503+
OpdsMapping[1] = getFPValueMapping(ScalarTy.getSizeInBits(), HasFPExt);
499504
} else
500505
OpdsMapping[1] = GPRValueMapping;
501506
break;
@@ -514,7 +519,7 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
514519
OpdsMapping[Idx] =
515520
getVRBValueMapping(Ty.getSizeInBits().getKnownMinValue());
516521
else if (isPreISelGenericFloatingPointOpcode(Opc))
517-
OpdsMapping[Idx] = getFPValueMapping(Ty.getSizeInBits());
522+
OpdsMapping[Idx] = getFPValueMapping(Ty.getSizeInBits(), HasFPExt);
518523
else
519524
OpdsMapping[Idx] = GPRValueMapping;
520525
}

‎llvm/test/CodeGen/RISCV/GlobalISel/constantpool.ll‎

Lines changed: 16 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -15,47 +15,37 @@
1515
define void @constpool_f32(ptr %p) {
1616
; RV32-SMALL-LABEL: constpool_f32:
1717
; RV32-SMALL: # %bb.0:
18-
; RV32-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
19-
; RV32-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
18+
; RV32-SMALL-NEXT: lui a1, 260096
2019
; RV32-SMALL-NEXT: sw a1, 0(a0)
2120
; RV32-SMALL-NEXT: ret
2221
;
2322
; RV32-MEDIUM-LABEL: constpool_f32:
2423
; RV32-MEDIUM: # %bb.0:
25-
; RV32-MEDIUM-NEXT: .Lpcrel_hi0:
26-
; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
27-
; RV32-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
24+
; RV32-MEDIUM-NEXT: lui a1, 260096
2825
; RV32-MEDIUM-NEXT: sw a1, 0(a0)
2926
; RV32-MEDIUM-NEXT: ret
3027
;
3128
; RV32-PIC-LABEL: constpool_f32:
3229
; RV32-PIC: # %bb.0:
33-
; RV32-PIC-NEXT: .Lpcrel_hi0:
34-
; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
35-
; RV32-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
30+
; RV32-PIC-NEXT: lui a1, 260096
3631
; RV32-PIC-NEXT: sw a1, 0(a0)
3732
; RV32-PIC-NEXT: ret
3833
;
3934
; RV64-SMALL-LABEL: constpool_f32:
4035
; RV64-SMALL: # %bb.0:
41-
; RV64-SMALL-NEXT: lui a1, %hi(.LCPI0_0)
42-
; RV64-SMALL-NEXT: lw a1, %lo(.LCPI0_0)(a1)
36+
; RV64-SMALL-NEXT: lui a1, 260096
4337
; RV64-SMALL-NEXT: sw a1, 0(a0)
4438
; RV64-SMALL-NEXT: ret
4539
;
4640
; RV64-MEDIUM-LABEL: constpool_f32:
4741
; RV64-MEDIUM: # %bb.0:
48-
; RV64-MEDIUM-NEXT: .Lpcrel_hi0:
49-
; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
50-
; RV64-MEDIUM-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
42+
; RV64-MEDIUM-NEXT: lui a1, 260096
5143
; RV64-MEDIUM-NEXT: sw a1, 0(a0)
5244
; RV64-MEDIUM-NEXT: ret
5345
;
5446
; RV64-PIC-LABEL: constpool_f32:
5547
; RV64-PIC: # %bb.0:
56-
; RV64-PIC-NEXT: .Lpcrel_hi0:
57-
; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI0_0)
58-
; RV64-PIC-NEXT: lw a1, %pcrel_lo(.Lpcrel_hi0)(a1)
48+
; RV64-PIC-NEXT: lui a1, 260096
5949
; RV64-PIC-NEXT: sw a1, 0(a0)
6050
; RV64-PIC-NEXT: ret
6151
store float 1.0, ptr %p
@@ -75,9 +65,9 @@ define void @constpool_f64(ptr %p) {
7565
;
7666
; RV32-MEDIUM-LABEL: constpool_f64:
7767
; RV32-MEDIUM: # %bb.0:
78-
; RV32-MEDIUM-NEXT: .Lpcrel_hi1:
68+
; RV32-MEDIUM-NEXT: .Lpcrel_hi0:
7969
; RV32-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
80-
; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
70+
; RV32-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi0)
8171
; RV32-MEDIUM-NEXT: lw a2, 0(a1)
8272
; RV32-MEDIUM-NEXT: lw a1, 4(a1)
8373
; RV32-MEDIUM-NEXT: sw a2, 0(a0)
@@ -86,9 +76,9 @@ define void @constpool_f64(ptr %p) {
8676
;
8777
; RV32-PIC-LABEL: constpool_f64:
8878
; RV32-PIC: # %bb.0:
89-
; RV32-PIC-NEXT: .Lpcrel_hi1:
79+
; RV32-PIC-NEXT: .Lpcrel_hi0:
9080
; RV32-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
91-
; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi1)
81+
; RV32-PIC-NEXT: addi a1, a1, %pcrel_lo(.Lpcrel_hi0)
9282
; RV32-PIC-NEXT: lw a2, 0(a1)
9383
; RV32-PIC-NEXT: lw a1, 4(a1)
9484
; RV32-PIC-NEXT: sw a2, 0(a0)
@@ -97,24 +87,22 @@ define void @constpool_f64(ptr %p) {
9787
;
9888
; RV64-SMALL-LABEL: constpool_f64:
9989
; RV64-SMALL: # %bb.0:
100-
; RV64-SMALL-NEXT: lui a1, %hi(.LCPI1_0)
101-
; RV64-SMALL-NEXT: ld a1, %lo(.LCPI1_0)(a1)
90+
; RV64-SMALL-NEXT: li a1, 1023
91+
; RV64-SMALL-NEXT: slli a1, a1, 52
10292
; RV64-SMALL-NEXT: sd a1, 0(a0)
10393
; RV64-SMALL-NEXT: ret
10494
;
10595
; RV64-MEDIUM-LABEL: constpool_f64:
10696
; RV64-MEDIUM: # %bb.0:
107-
; RV64-MEDIUM-NEXT: .Lpcrel_hi1:
108-
; RV64-MEDIUM-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
109-
; RV64-MEDIUM-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
97+
; RV64-MEDIUM-NEXT: li a1, 1023
98+
; RV64-MEDIUM-NEXT: slli a1, a1, 52
11099
; RV64-MEDIUM-NEXT: sd a1, 0(a0)
111100
; RV64-MEDIUM-NEXT: ret
112101
;
113102
; RV64-PIC-LABEL: constpool_f64:
114103
; RV64-PIC: # %bb.0:
115-
; RV64-PIC-NEXT: .Lpcrel_hi1:
116-
; RV64-PIC-NEXT: auipc a1, %pcrel_hi(.LCPI1_0)
117-
; RV64-PIC-NEXT: ld a1, %pcrel_lo(.Lpcrel_hi1)(a1)
104+
; RV64-PIC-NEXT: li a1, 1023
105+
; RV64-PIC-NEXT: slli a1, a1, 52
118106
; RV64-PIC-NEXT: sd a1, 0(a0)
119107
; RV64-PIC-NEXT: ret
120108
store double 1.0, ptr %p

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