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[Hexagon] Remove implicit conversions of MCRegister to unsigned. NFC (#167571)
Use MCRegister instead of unsigned or use MCRegister::id()
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3 files changed

+30
-30
lines changed

3 files changed

+30
-30
lines changed

llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -463,7 +463,7 @@ void HexagonOperand::print(raw_ostream &OS, const MCAsmInfo &MAI) const {
463463
break;
464464
case Register:
465465
OS << "<register R";
466-
OS << getReg() << ">";
466+
OS << getReg().id() << ">";
467467
break;
468468
case Token:
469469
OS << "'" << getToken() << "'";

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -385,7 +385,7 @@ bool HexagonMCChecker::checkSlots() {
385385
bool HexagonMCChecker::checkPredicates() {
386386
// Check for proper use of new predicate registers.
387387
for (const auto &I : NewPreds) {
388-
unsigned P = I;
388+
MCRegister P = I;
389389

390390
if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) {
391391
// Error out if the new predicate register is not defined,
@@ -398,7 +398,7 @@ bool HexagonMCChecker::checkPredicates() {
398398

399399
// Check for proper use of auto-anded of predicate registers.
400400
for (const auto &I : LatePreds) {
401-
unsigned P = I;
401+
MCRegister P = I;
402402

403403
if (LatePreds.count(P) > 1 || Defs.count(P)) {
404404
// Error out if predicate register defined "late" multiple times or
@@ -607,7 +607,7 @@ void HexagonMCChecker::checkRegisterCurDefs() {
607607
bool HexagonMCChecker::checkRegisters() {
608608
// Check for proper register definitions.
609609
for (const auto &I : Defs) {
610-
unsigned R = I.first;
610+
MCRegister R = I.first;
611611

612612
if (isLoopRegister(R) && Defs.count(R) > 1 &&
613613
(HexagonMCInstrInfo::isInnerLoop(MCB) ||
@@ -620,8 +620,8 @@ bool HexagonMCChecker::checkRegisters() {
620620
if (SoftDefs.count(R)) {
621621
// Error out for explicit changes to registers also weakly defined
622622
// (e.g., "{ usr = r0; r0 = sfadd(...) }").
623-
unsigned UsrR = Hexagon::USR; // Silence warning about mixed types in ?:.
624-
unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
623+
MCRegister UsrR = Hexagon::USR;
624+
MCRegister BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
625625
reportErrorRegisters(BadR);
626626
return false;
627627
}
@@ -633,8 +633,8 @@ bool HexagonMCChecker::checkRegisters() {
633633
if (PM.count(Unconditional)) {
634634
// Error out on an unconditional change when there are any other
635635
// changes, conditional or not.
636-
unsigned UsrR = Hexagon::USR;
637-
unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
636+
MCRegister UsrR = Hexagon::USR;
637+
MCRegister BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R;
638638
reportErrorRegisters(BadR);
639639
return false;
640640
}
@@ -664,7 +664,7 @@ bool HexagonMCChecker::checkRegisters() {
664664

665665
// Check for use of temporary definitions.
666666
for (const auto &I : TmpDefs) {
667-
unsigned R = I;
667+
MCRegister R = I;
668668

669669
if (!Uses.count(R)) {
670670
// special case for vhist
@@ -765,12 +765,12 @@ void HexagonMCChecker::compoundRegisterMap(unsigned &Register) {
765765
}
766766
}
767767

768-
void HexagonMCChecker::reportErrorRegisters(unsigned Register) {
768+
void HexagonMCChecker::reportErrorRegisters(MCRegister Register) {
769769
reportError("register `" + Twine(RI.getName(Register)) +
770770
"' modified more than once");
771771
}
772772

773-
void HexagonMCChecker::reportErrorNewValue(unsigned Register) {
773+
void HexagonMCChecker::reportErrorNewValue(MCRegister Register) {
774774
reportError("register `" + Twine(RI.getName(Register)) +
775775
"' used with `.new' "
776776
"but not validly modified in the same packet");

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -39,41 +39,41 @@ class HexagonMCChecker {
3939
bool ReportErrors;
4040

4141
/// Set of definitions: register #, if predicated, if predicated true.
42-
using PredSense = std::pair<unsigned, bool>;
42+
using PredSense = std::pair<MCRegister, bool>;
4343
static const PredSense Unconditional;
4444
using PredSet = std::multiset<PredSense>;
4545
using PredSetIterator = std::multiset<PredSense>::iterator;
4646

47-
using DefsIterator = DenseMap<unsigned, PredSet>::iterator;
48-
DenseMap<unsigned, PredSet> Defs;
47+
using DefsIterator = DenseMap<MCRegister, PredSet>::iterator;
48+
DenseMap<MCRegister, PredSet> Defs;
4949

5050
/// Set of weak definitions whose clashes should be enforced selectively.
51-
using SoftDefsIterator = std::set<unsigned>::iterator;
52-
std::set<unsigned> SoftDefs;
51+
using SoftDefsIterator = std::set<MCRegister>::iterator;
52+
std::set<MCRegister> SoftDefs;
5353

5454
/// Set of temporary definitions not committed to the register file.
55-
using TmpDefsIterator = std::set<unsigned>::iterator;
56-
std::set<unsigned> TmpDefs;
55+
using TmpDefsIterator = std::set<MCRegister>::iterator;
56+
std::set<MCRegister> TmpDefs;
5757

5858
/// Set of new predicates used.
59-
using NewPredsIterator = std::set<unsigned>::iterator;
60-
std::set<unsigned> NewPreds;
59+
using NewPredsIterator = std::set<MCRegister>::iterator;
60+
std::set<MCRegister> NewPreds;
6161

6262
/// Set of predicates defined late.
63-
using LatePredsIterator = std::multiset<unsigned>::iterator;
64-
std::multiset<unsigned> LatePreds;
63+
using LatePredsIterator = std::multiset<MCRegister>::iterator;
64+
std::multiset<MCRegister> LatePreds;
6565

6666
/// Set of uses.
67-
using UsesIterator = std::set<unsigned>::iterator;
68-
std::set<unsigned> Uses;
67+
using UsesIterator = std::set<MCRegister>::iterator;
68+
std::set<MCRegister> Uses;
6969

7070
/// Pre-defined set of read-only registers.
71-
using ReadOnlyIterator = std::set<unsigned>::iterator;
72-
std::set<unsigned> ReadOnly;
71+
using ReadOnlyIterator = std::set<MCRegister>::iterator;
72+
std::set<MCRegister> ReadOnly;
7373

7474
// Contains the vector-pair-registers with the even number
7575
// first ("v0:1", e.g.) used/def'd in this packet.
76-
std::set<unsigned> ReversePairs;
76+
std::set<MCRegister> ReversePairs;
7777

7878
void init();
7979
void init(MCInst const &);
@@ -107,7 +107,7 @@ class HexagonMCChecker {
107107

108108
static void compoundRegisterMap(unsigned &);
109109

110-
bool isLoopRegister(unsigned R) const {
110+
bool isLoopRegister(MCRegister R) const {
111111
return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R ||
112112
Hexagon::LC1 == R);
113113
}
@@ -120,8 +120,8 @@ class HexagonMCChecker {
120120
MCSubtargetInfo const &STI, bool CopyReportErrors);
121121

122122
bool check(bool FullCheck = true);
123-
void reportErrorRegisters(unsigned Register);
124-
void reportErrorNewValue(unsigned Register);
123+
void reportErrorRegisters(MCRegister Register);
124+
void reportErrorNewValue(MCRegister Register);
125125
void reportError(SMLoc Loc, Twine const &Msg);
126126
void reportNote(SMLoc Loc, Twine const &Msg);
127127
void reportError(Twine const &Msg);

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