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ValueTracking: pre-commit tests for Div/Rem recurrence
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‎llvm/test/Analysis/ValueTracking/recurrence-knownbits.ll‎

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Original file line numberDiff line numberDiff line change
@@ -81,6 +81,236 @@ exit:
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ret i64 %res
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}
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define i64 @test_udiv(i1 %c) {
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; CHECK-LABEL: @test_udiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = udiv i64 [[IV]], 3
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [9, %entry], [%iv.next, %loop]
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%iv.next = udiv i64 %iv, 3
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, 16
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ret i64 %res
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}
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define i64 @test_sdiv(i1 %c) {
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; CHECK-LABEL: @test_sdiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = sdiv i64 [[IV]], -3
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [-9, %entry], [%iv.next, %loop]
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%iv.next = sdiv i64 %iv, -3
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, 16
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ret i64 %res
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}
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define i64 @test_sdiv2(i1 %c) {
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; CHECK-LABEL: @test_sdiv2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = sdiv i64 [[IV]], 3
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [-9, %entry], [%iv.next, %loop]
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%iv.next = sdiv i64 %iv, 3
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, 16
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ret i64 %res
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}
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define i64 @test_sdiv3(i1 %c) {
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; CHECK-LABEL: @test_sdiv3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = sdiv i64 [[IV]], -3
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], -16
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [9, %entry], [%iv.next, %loop]
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%iv.next = sdiv i64 %iv, -3
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, -16
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ret i64 %res
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}
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define i64 @test_urem(i1 %c) {
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; CHECK-LABEL: @test_urem(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 3, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = urem i64 9, [[IV]]
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 4
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [3, %entry], [%iv.next, %loop]
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%iv.next = urem i64 9, %iv
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, 4
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ret i64 %res
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}
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define i64 @test_srem(i1 %c) {
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; CHECK-LABEL: @test_srem(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = srem i64 [[IV]], 3
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [-9, %entry], [%iv.next, %loop]
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%iv.next = srem i64 %iv, -3
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, 16
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ret i64 %res
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}
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define i64 @test_srem2(i1 %c) {
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; CHECK-LABEL: @test_srem2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = srem i64 [[IV]], 3
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 16
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [-9, %entry], [%iv.next, %loop]
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%iv.next = srem i64 %iv, 3
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, 16
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ret i64 %res
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}
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define i64 @test_srem2_flipped(i1 %c) {
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; CHECK-LABEL: @test_srem2_flipped(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 3, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = srem i64 -9, [[IV]]
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], 4
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [3, %entry], [%iv.next, %loop]
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%iv.next = srem i64 -9, %iv
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, 4
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ret i64 %res
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}
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define i64 @test_srem3(i1 %c) {
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; CHECK-LABEL: @test_srem3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 9, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = srem i64 [[IV]], 3
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], -16
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [9, %entry], [%iv.next, %loop]
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%iv.next = srem i64 %iv, -3
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, -16
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ret i64 %res
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}
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define i64 @test_srem3_flipped(i1 %c) {
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; CHECK-LABEL: @test_srem3_flipped(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ -3, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = srem i64 9, [[IV]]
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; CHECK-NEXT: br i1 [[C:%.*]], label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = and i64 [[IV]], -4
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [-3, %entry], [%iv.next, %loop]
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%iv.next = srem i64 9, %iv
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br i1 %c, label %exit, label %loop
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exit:
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%res = and i64 %iv, -4
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ret i64 %res
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}
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define i64 @test_and(i1 %c) {
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; CHECK-LABEL: @test_and(
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; CHECK-NEXT: entry:

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