@@ -100,9 +100,6 @@ namespace {
100100 void getAnalysisUsage (AnalysisUsage &AU) const override {
101101 MachineFunctionPass::getAnalysisUsage (AU);
102102 }
103-
104- private:
105- void ChangeOpInto (MachineOperand &Dst, MachineOperand &Src);
106103 };
107104}
108105
@@ -132,7 +129,9 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
132129 PeepholeDoubleRegsMap.clear ();
133130
134131 // Traverse the basic block.
135- for (MachineInstr &MI : *MBB) {
132+ for (auto I = MBB->begin (), E = MBB->end (), NextI = I; I != E; I = NextI) {
133+ NextI = std::next (I);
134+ MachineInstr &MI = *I;
136135 // Look for sign extends:
137136 // %vreg170<def> = SXTW %vreg166
138137 if (!DisableOptSZExt && MI.getOpcode () == Hexagon::A2_sxtw) {
@@ -280,14 +279,13 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
280279 if (NewOp) {
281280 unsigned PSrc = MI.getOperand (PR).getReg ();
282281 if (unsigned POrig = PeepholeMap.lookup (PSrc)) {
283- MI.getOperand (PR).setReg (POrig);
282+ BuildMI (*MBB, MI.getIterator (), MI.getDebugLoc (),
283+ QII->get (NewOp), MI.getOperand (0 ).getReg ())
284+ .addReg (POrig)
285+ .add (MI.getOperand (S2))
286+ .add (MI.getOperand (S1));
284287 MRI->clearKillFlags (POrig);
285- MI.setDesc (QII->get (NewOp));
286- // Swap operands S1 and S2.
287- MachineOperand Op1 = MI.getOperand (S1);
288- MachineOperand Op2 = MI.getOperand (S2);
289- ChangeOpInto (MI.getOperand (S1), Op2);
290- ChangeOpInto (MI.getOperand (S2), Op1);
288+ MI.eraseFromParent ();
291289 }
292290 } // if (NewOp)
293291 } // if (!Done)
@@ -299,40 +297,6 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
299297 return true ;
300298}
301299
302- void HexagonPeephole::ChangeOpInto (MachineOperand &Dst, MachineOperand &Src) {
303- assert (&Dst != &Src && " Cannot duplicate into itself" );
304- switch (Dst.getType ()) {
305- case MachineOperand::MO_Register:
306- if (Src.isReg ()) {
307- Dst.setReg (Src.getReg ());
308- Dst.setSubReg (Src.getSubReg ());
309- MRI->clearKillFlags (Src.getReg ());
310- } else if (Src.isImm ()) {
311- Dst.ChangeToImmediate (Src.getImm ());
312- } else {
313- llvm_unreachable (" Unexpected src operand type" );
314- }
315- break ;
316-
317- case MachineOperand::MO_Immediate:
318- if (Src.isImm ()) {
319- Dst.setImm (Src.getImm ());
320- } else if (Src.isReg ()) {
321- Dst.ChangeToRegister (Src.getReg (), Src.isDef (), Src.isImplicit (),
322- false , Src.isDead (), Src.isUndef (),
323- Src.isDebug ());
324- Dst.setSubReg (Src.getSubReg ());
325- } else {
326- llvm_unreachable (" Unexpected src operand type" );
327- }
328- break ;
329-
330- default :
331- llvm_unreachable (" Unexpected dst operand type" );
332- break ;
333- }
334- }
335-
336300FunctionPass *llvm::createHexagonPeephole () {
337301 return new HexagonPeephole ();
338302}
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