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Ensure ensure all subvector uses are replaced
1 parent 1e18162 commit 5b93950

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2 files changed

+524
-538
lines changed

2 files changed

+524
-538
lines changed

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58562,16 +58562,22 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
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// If we're splatting the lower half subvector of a full vector load into the
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// upper half, attempt to create a subvector broadcast.
58565+
// TODO: Drop hasOneUse checks.
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if (IdxVal == (OpVT.getVectorNumElements() / 2) &&
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Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits()) &&
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(Vec.hasOneUse() || SubVec.hasOneUse())) {
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auto *VecLd = dyn_cast<LoadSDNode>(Vec);
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auto *SubLd = dyn_cast<LoadSDNode>(SubVec);
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if (VecLd && SubLd &&
58571-
DAG.areNonVolatileConsecutiveLoads(SubLd, VecLd,
58572-
SubVec.getValueSizeInBits() / 8, 0))
58573-
return getBROADCAST_LOAD(X86ISD::SUBV_BROADCAST_LOAD, dl, OpVT, SubVecVT,
58574-
SubLd, 0, DAG);
58572+
DAG.areNonVolatileConsecutiveLoads(
58573+
SubLd, VecLd, SubVec.getValueSizeInBits() / 8, 0)) {
58574+
SDValue BcastLd = getBROADCAST_LOAD(X86ISD::SUBV_BROADCAST_LOAD, dl, OpVT,
58575+
SubVecVT, SubLd, 0, DAG);
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SDValue NewSubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT,
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BcastLd, DAG.getVectorIdxConstant(0, dl));
58578+
DCI.CombineTo(SubLd, NewSubVec, BcastLd.getValue(1));
58579+
return BcastLd;
58580+
}
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}
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return SDValue();

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