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1 parent 1f0af01 commit 5b93d4dCopy full SHA for 5b93d4d
mlir/test/Dialect/LLVMIR/roundtrip.mlir
@@ -1001,4 +1001,4 @@ llvm.func @intrinsic_call_arg_attrs_bundles(%arg0: i32) -> i32 {
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// CHECK: %{{.*}} = llvm.call_intrinsic "llvm.riscv.sha256sig0"({{.*}}) ["adazdazd"()] {constant} : (i32 {llvm.signext}) -> i32
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%0 = llvm.call_intrinsic "llvm.riscv.sha256sig0"(%arg0) ["adazdazd"()] {constant} : (i32 {llvm.signext}) -> (i32)
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llvm.return %0 : i32
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-}
+}
mlir/test/Target/LLVMIR/Import/intrinsic-unregistered.ll
@@ -76,4 +76,4 @@ define signext i32 @test_intrin_arg_attr(i32 signext %a) nounwind {
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; CHECK: llvm.call_intrinsic "llvm.riscv.sha256sig0"({{.*}}) : (i32 {llvm.signext}) -> i32
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%val = call i32 @llvm.riscv.sha256sig0(i32 signext %a)
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ret i32 %val
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