Invoking the fmulCombine in both the AMDGPUPreLegalCombine and AMDGPUPostLegalCombiner.

Author: vg0204

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

@@ -125,14 +125,14 @@ def sign_extension_in_reg : GICombineRule<
   (apply [{ applyCombineSignExtendInReg(*${sign_inreg}, ${matchinfo}); }])>;
 
 // Do the following combines :
-// fmul x, select(y, A, B)   -> ldexp (x, select i32 (y, a, b))
-// fmul x, select(y, -A, -B) -> ldexp ((fneg x), select i32 (y, a, b))
-def combine_fmul_with_select_to_ldexp : GICombineRule<
+// fmul x, select(y, A, B)   -> fldexp (x, select i32 (y, a, b))
+// fmul x, select(y, -A, -B) -> fldexp ((fneg x), select i32 (y, a, b))
+def combine_fmul_with_select_to_fldexp : GICombineRule<
   (defs root:$root, build_fn_matchinfo:$matchinfo),
   (match  (G_FMUL $dst, $x, $select):$root,
           (G_SELECT $select, $y, $A, $B):$sel,
-          [{ return Helper.matchCombineFmulWithSelectToLdexp(*${root}, *${sel}, ${matchinfo}); }]),
-  (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
+          [{ return Helper.matchCombineFmulWithSelectToFldexp(*${root}, *${sel}, ${matchinfo}); }]),
+  (apply  [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
 
 
 let Predicates = [Has16BitInsts, NotHasMed3_16] in {
@@ -163,13 +163,13 @@ def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
 
 def AMDGPUPreLegalizerCombiner: GICombiner<
   "AMDGPUPreLegalizerCombinerImpl",
-  [all_combines, clamp_i64_to_i16, foldable_fneg]> {
+  [all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16, foldable_fneg]> {
   let CombineAllMethodName = "tryCombineAllImpl";
 }
 
 def AMDGPUPostLegalizerCombiner: GICombiner<
   "AMDGPUPostLegalizerCombinerImpl",
-  [all_combines, gfx6gfx7_combines, gfx8_combines,
+  [all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
    uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
    rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64]> {
   let CombineAllMethodName = "tryCombineAllImpl";

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp

@@ -446,7 +446,7 @@ void AMDGPUCombinerHelper::applyExpandPromotedF16FMed3(MachineInstr &MI,
   MI.eraseFromParent();
 }
 
-bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToLdexp(
+bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToFldexp(
     MachineInstr &MI, MachineInstr &Sel,
     std::function<void(MachineIRBuilder &)> &MatchInfo) {
   assert(MI.getOpcode() == TargetOpcode::G_FMUL);
@@ -465,13 +465,13 @@ bool AMDGPUCombinerHelper::matchCombineFmulWithSelectToLdexp(
 
     const auto SelectTrueCst =
         DestTy.isVector()
-            ? getFConstantSplat(SelectTrue, MRI, /* allowUndef */ true)
+            ? getFConstantSplat(SelectTrue, MRI, /*allowUndef=*/false)
             : getFConstantVRegValWithLookThrough(SelectTrue, MRI);
     if (!SelectTrueCst)
       return false;
     const auto SelectFalseCst =
         DestTy.isVector()
-            ? getFConstantSplat(SelectFalse, MRI, /* allowUndef */ true)
+            ? getFConstantSplat(SelectFalse, MRI, /*allowUndef=*/false)
             : getFConstantVRegValWithLookThrough(SelectFalse, MRI);
     if (!SelectFalseCst)
       return false;

llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.h

@@ -31,7 +31,7 @@ class AMDGPUCombinerHelper : public CombinerHelper {
   void applyExpandPromotedF16FMed3(MachineInstr &MI, Register Src0,
                                    Register Src1, Register Src2);
 
-  bool matchCombineFmulWithSelectToLdexp(
+  bool matchCombineFmulWithSelectToFldexp(
       MachineInstr &MI, MachineInstr &Sel,
       std::function<void(MachineIRBuilder &)> &MatchInfo);
 };