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eugeniseugenis
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Revert "Overflow and saturating intrinsics (#88068)"
This reverts commit 118a5d8.
1 parent ec1af63 commit 5bc87da

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3 files changed

+75
-78
lines changed

3 files changed

+75
-78
lines changed

‎llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp‎

Lines changed: 0 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -3715,37 +3715,8 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
37153715
setOrigin(&I, getOrigin(&I, 0));
37163716
}
37173717

3718-
void handleArithmeticWithOverflow(IntrinsicInst &I) {
3719-
IRBuilder<> IRB(&I);
3720-
Value *Shadow0 = IRB.CreateOr(getShadow(&I, 0), getShadow(&I, 1));
3721-
Value *Shadow1 = IRB.CreateICmpNE(Shadow0, getCleanShadow(Shadow0));
3722-
3723-
Value *Shadow = PoisonValue::get(getShadowTy(&I));
3724-
Shadow = IRB.CreateInsertValue(Shadow, Shadow0, 0);
3725-
Shadow = IRB.CreateInsertValue(Shadow, Shadow1, 1);
3726-
3727-
setShadow(&I, Shadow);
3728-
setOriginForNaryOp(I);
3729-
}
3730-
37313718
void visitIntrinsicInst(IntrinsicInst &I) {
37323719
switch (I.getIntrinsicID()) {
3733-
case Intrinsic::uadd_with_overflow:
3734-
case Intrinsic::sadd_with_overflow:
3735-
case Intrinsic::usub_with_overflow:
3736-
case Intrinsic::ssub_with_overflow:
3737-
case Intrinsic::umul_with_overflow:
3738-
case Intrinsic::smul_with_overflow:
3739-
handleArithmeticWithOverflow(I);
3740-
break;
3741-
case Intrinsic::sadd_sat:
3742-
case Intrinsic::uadd_sat:
3743-
case Intrinsic::ssub_sat:
3744-
case Intrinsic::usub_sat:
3745-
case Intrinsic::sshl_sat:
3746-
case Intrinsic::ushl_sat:
3747-
handleShadowOr(I);
3748-
break;
37493720
case Intrinsic::abs:
37503721
handleAbsIntrinsic(I);
37513722
break;

‎llvm/test/Instrumentation/MemorySanitizer/overflow.ll‎

Lines changed: 68 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -10,12 +10,16 @@ define {i64, i1} @test_sadd_with_overflow(i64 %a, i64 %b) #0 {
1010
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
1111
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
1212
; CHECK-NEXT: call void @llvm.donothing()
13-
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]]
14-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
15-
; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0
16-
; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1
13+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
14+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
15+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
16+
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0:![0-9]+]]
17+
; CHECK: 3:
18+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]
19+
; CHECK-NEXT: unreachable
20+
; CHECK: 4:
1721
; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 [[A]], i64 [[B]])
18-
; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8
22+
; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
1923
; CHECK-NEXT: ret { i64, i1 } [[RES]]
2024
;
2125
%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b)
@@ -28,12 +32,16 @@ define {i64, i1} @test_uadd_with_overflow(i64 %a, i64 %b) #0 {
2832
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
2933
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
3034
; CHECK-NEXT: call void @llvm.donothing()
31-
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]]
32-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
33-
; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0
34-
; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1
35+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
36+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
37+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
38+
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
39+
; CHECK: 3:
40+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
41+
; CHECK-NEXT: unreachable
42+
; CHECK: 4:
3543
; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 [[A]], i64 [[B]])
36-
; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8
44+
; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
3745
; CHECK-NEXT: ret { i64, i1 } [[RES]]
3846
;
3947
%res = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
@@ -46,12 +54,16 @@ define {i64, i1} @test_smul_with_overflow(i64 %a, i64 %b) #0 {
4654
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
4755
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
4856
; CHECK-NEXT: call void @llvm.donothing()
49-
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]]
50-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
51-
; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0
52-
; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1
57+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
58+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
59+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
60+
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
61+
; CHECK: 3:
62+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
63+
; CHECK-NEXT: unreachable
64+
; CHECK: 4:
5365
; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 [[A]], i64 [[B]])
54-
; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8
66+
; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
5567
; CHECK-NEXT: ret { i64, i1 } [[RES]]
5668
;
5769
%res = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %a, i64 %b)
@@ -63,12 +75,16 @@ define {i64, i1} @test_umul_with_overflow(i64 %a, i64 %b) #0 {
6375
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
6476
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
6577
; CHECK-NEXT: call void @llvm.donothing()
66-
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]]
67-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
68-
; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0
69-
; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1
78+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
79+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
80+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
81+
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
82+
; CHECK: 3:
83+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
84+
; CHECK-NEXT: unreachable
85+
; CHECK: 4:
7086
; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 [[A]], i64 [[B]])
71-
; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8
87+
; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
7288
; CHECK-NEXT: ret { i64, i1 } [[RES]]
7389
;
7490
%res = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 %b)
@@ -80,12 +96,16 @@ define {i64, i1} @test_ssub_with_overflow(i64 %a, i64 %b) #0 {
8096
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
8197
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
8298
; CHECK-NEXT: call void @llvm.donothing()
83-
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]]
84-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
85-
; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0
86-
; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1
99+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
100+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
101+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
102+
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
103+
; CHECK: 3:
104+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
105+
; CHECK-NEXT: unreachable
106+
; CHECK: 4:
87107
; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 [[A]], i64 [[B]])
88-
; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8
108+
; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
89109
; CHECK-NEXT: ret { i64, i1 } [[RES]]
90110
;
91111
%res = call { i64, i1 } @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)
@@ -97,12 +117,16 @@ define {i64, i1} @test_usub_with_overflow(i64 %a, i64 %b) #0 {
97117
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8
98118
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
99119
; CHECK-NEXT: call void @llvm.donothing()
100-
; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP1]], [[TMP2]]
101-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP3]], 0
102-
; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP3]], 0
103-
; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { i64, i1 } [[TMP5]], i1 [[TMP4]], 1
120+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0
121+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 0
122+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
123+
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
124+
; CHECK: 3:
125+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
126+
; CHECK-NEXT: unreachable
127+
; CHECK: 4:
104128
; CHECK-NEXT: [[RES:%.*]] = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 [[A]], i64 [[B]])
105-
; CHECK-NEXT: store { i64, i1 } [[TMP6]], ptr @__msan_retval_tls, align 8
129+
; CHECK-NEXT: store { i64, i1 } zeroinitializer, ptr @__msan_retval_tls, align 8
106130
; CHECK-NEXT: ret { i64, i1 } [[RES]]
107131
;
108132
%res = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %b)
@@ -115,16 +139,25 @@ define {<4 x i32>, <4 x i1>} @test_sadd_with_overflow_vec(<4 x i32> %a, <4 x i32
115139
; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8
116140
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
117141
; CHECK-NEXT: call void @llvm.donothing()
118-
; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]
119-
; CHECK-NEXT: [[TMP4:%.*]] = icmp ne <4 x i32> [[TMP3]], zeroinitializer
120-
; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { <4 x i32>, <4 x i1> } poison, <4 x i32> [[TMP3]], 0
121-
; CHECK-NEXT: [[TMP6:%.*]] = insertvalue { <4 x i32>, <4 x i1> } [[TMP5]], <4 x i1> [[TMP4]], 1
142+
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128
143+
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0
144+
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128
145+
; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0
146+
; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]
147+
; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]]
148+
; CHECK: 5:
149+
; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]
150+
; CHECK-NEXT: unreachable
151+
; CHECK: 6:
122152
; CHECK-NEXT: [[RES:%.*]] = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> [[A]], <4 x i32> [[B]])
123-
; CHECK-NEXT: store { <4 x i32>, <4 x i1> } [[TMP6]], ptr @__msan_retval_tls, align 8
153+
; CHECK-NEXT: store { <4 x i32>, <4 x i1> } zeroinitializer, ptr @__msan_retval_tls, align 8
124154
; CHECK-NEXT: ret { <4 x i32>, <4 x i1> } [[RES]]
125155
;
126156
%res = call { <4 x i32>, <4 x i1> } @llvm.sadd.with.overflow.v4i32(<4 x i32> %a, <4 x i32> %b)
127157
ret { <4 x i32>, <4 x i1> } %res
128158
}
129159

130160
attributes #0 = { sanitize_memory }
161+
;.
162+
; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1000}
163+
;.

‎llvm/test/Instrumentation/MemorySanitizer/saturating.ll‎

Lines changed: 7 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,8 @@ define i64 @test_sadd_sat(i64 %a, i64 %b) #0 {
1111
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
1212
; CHECK-NEXT: call void @llvm.donothing()
1313
; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
14-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0
1514
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sadd.sat.i64(i64 [[A]], i64 [[B]])
16-
; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8
15+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
1716
; CHECK-NEXT: ret i64 [[RES]]
1817
;
1918
%res = call i64 @llvm.sadd.sat(i64 %a, i64 %b)
@@ -27,9 +26,8 @@ define i64 @test_uadd_sat(i64 %a, i64 %b) #0 {
2726
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
2827
; CHECK-NEXT: call void @llvm.donothing()
2928
; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
30-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0
3129
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[A]], i64 [[B]])
32-
; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8
30+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
3331
; CHECK-NEXT: ret i64 [[RES]]
3432
;
3533
%res = call i64 @llvm.uadd.sat(i64 %a, i64 %b)
@@ -43,9 +41,8 @@ define i64 @test_ssub_sat(i64 %a, i64 %b) #0 {
4341
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
4442
; CHECK-NEXT: call void @llvm.donothing()
4543
; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
46-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0
4744
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ssub.sat.i64(i64 [[A]], i64 [[B]])
48-
; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8
45+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
4946
; CHECK-NEXT: ret i64 [[RES]]
5047
;
5148
%res = call i64 @llvm.ssub.sat(i64 %a, i64 %b)
@@ -59,9 +56,8 @@ define i64 @test_usub_sat(i64 %a, i64 %b) #0 {
5956
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
6057
; CHECK-NEXT: call void @llvm.donothing()
6158
; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
62-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0
6359
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.usub.sat.i64(i64 [[A]], i64 [[B]])
64-
; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8
60+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
6561
; CHECK-NEXT: ret i64 [[RES]]
6662
;
6763
%res = call i64 @llvm.usub.sat(i64 %a, i64 %b)
@@ -75,9 +71,8 @@ define i64 @test_sshl_sat(i64 %a, i64 %b) #0 {
7571
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
7672
; CHECK-NEXT: call void @llvm.donothing()
7773
; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
78-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0
7974
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.sshl.sat.i64(i64 [[A]], i64 [[B]])
80-
; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8
75+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
8176
; CHECK-NEXT: ret i64 [[RES]]
8277
;
8378
%res = call i64 @llvm.sshl.sat(i64 %a, i64 %b)
@@ -91,9 +86,8 @@ define i64 @test_ushl_sat(i64 %a, i64 %b) #0 {
9186
; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
9287
; CHECK-NEXT: call void @llvm.donothing()
9388
; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]
94-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 0
9589
; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ushl.sat.i64(i64 [[A]], i64 [[B]])
96-
; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 8
90+
; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8
9791
; CHECK-NEXT: ret i64 [[RES]]
9892
;
9993
%res = call i64 @llvm.ushl.sat(i64 %a, i64 %b)
@@ -107,9 +101,8 @@ define <4 x i32> @test_sadd_sat_vec(<4 x i32> %a, <4 x i32> %b) #0 {
107101
; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8
108102
; CHECK-NEXT: call void @llvm.donothing()
109103
; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], [[TMP2]]
110-
; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[_MSPROP]], zeroinitializer
111104
; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> [[A]], <4 x i32> [[B]])
112-
; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 8
105+
; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8
113106
; CHECK-NEXT: ret <4 x i32> [[RES]]
114107
;
115108
%res = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %a, <4 x i32> %b)

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