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[AArch64][GlobalISel] Add GISel coverage for i32 lround and lrint. NFC
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4 files changed

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4 files changed

+151
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‎llvm/test/CodeGen/AArch64/lrint-conv-fp16-win.ll‎

Lines changed: 29 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,49 @@
1-
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for testmhhs
6+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhws
7+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhxs
28

3-
; CHECK-LABEL: testmhhs:
4-
; CHECK: frintx h0, h0
5-
; CHECK-NEXT: fcvtzs w0, h0
6-
; CHECK-NEXT: ret
79
define i16 @testmhhs(half %x) {
10+
; CHECK-LABEL: testmhhs:
11+
; CHECK: // %bb.0: // %entry
12+
; CHECK-NEXT: fcvt s0, h0
13+
; CHECK-NEXT: frintx s0, s0
14+
; CHECK-NEXT: fcvtzs w0, s0
15+
; CHECK-NEXT: ret
816
entry:
917
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
1018
%conv = trunc i32 %0 to i16
1119
ret i16 %conv
1220
}
1321

14-
; CHECK-LABEL: testmhws:
15-
; CHECK: frintx h0, h0
16-
; CHECK-NEXT: fcvtzs w0, h0
17-
; CHECK-NEXT: ret
1822
define i32 @testmhws(half %x) {
23+
; CHECK-LABEL: testmhws:
24+
; CHECK: // %bb.0: // %entry
25+
; CHECK-NEXT: fcvt s0, h0
26+
; CHECK-NEXT: frintx s0, s0
27+
; CHECK-NEXT: fcvtzs w0, s0
28+
; CHECK-NEXT: ret
1929
entry:
2030
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
2131
ret i32 %0
2232
}
2333

24-
; CHECK-LABEL: testmhxs:
25-
; CHECK: frintx h0, h0
26-
; CHECK-NEXT: fcvtzs w8, h0
27-
; CHECK-NEXT: sxtw x0, w8
28-
; CHECK-NEXT: ret
2934
define i64 @testmhxs(half %x) {
35+
; CHECK-LABEL: testmhxs:
36+
; CHECK: // %bb.0: // %entry
37+
; CHECK-NEXT: fcvt s0, h0
38+
; CHECK-NEXT: frintx s0, s0
39+
; CHECK-NEXT: fcvtzs w8, s0
40+
; CHECK-NEXT: sxtw x0, w8
41+
; CHECK-NEXT: ret
3042
entry:
3143
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
3244
%conv = sext i32 %0 to i64
3345
ret i64 %conv
3446
}
35-
36-
declare i32 @llvm.lrint.i32.f16(half) nounwind readnone
47+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
48+
; CHECK-GI: {{.*}}
49+
; CHECK-SD: {{.*}}

‎llvm/test/CodeGen/AArch64/lrint-conv-win.ll‎

Lines changed: 33 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,48 +1,59 @@
1-
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for testmsxs
6+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsws
7+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsxd
8+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmswd
29

3-
; CHECK-LABEL: testmsxs:
4-
; CHECK: frintx [[SREG:s[0-9]+]], s0
5-
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
6-
; CHECK-NEXT: sxtw x0, [[WREG]]
7-
; CHECK-NEXT: ret
810
define i64 @testmsxs(float %x) {
11+
; CHECK-LABEL: testmsxs:
12+
; CHECK: // %bb.0: // %entry
13+
; CHECK-NEXT: frintx s0, s0
14+
; CHECK-NEXT: fcvtzs w8, s0
15+
; CHECK-NEXT: sxtw x0, w8
16+
; CHECK-NEXT: ret
917
entry:
1018
%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
1119
%conv = sext i32 %0 to i64
1220
ret i64 %conv
1321
}
1422

15-
; CHECK-LABEL: testmsws:
16-
; CHECK: frintx [[SREG:s[0-9]+]], s0
17-
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[SREG]]
18-
; CHECK-NEXT: ret
1923
define i32 @testmsws(float %x) {
24+
; CHECK-LABEL: testmsws:
25+
; CHECK: // %bb.0: // %entry
26+
; CHECK-NEXT: frintx s0, s0
27+
; CHECK-NEXT: fcvtzs w0, s0
28+
; CHECK-NEXT: ret
2029
entry:
2130
%0 = tail call i32 @llvm.lrint.i32.f32(float %x)
2231
ret i32 %0
2332
}
2433

25-
; CHECK-LABEL: testmsxd:
26-
; CHECK: frintx [[DREG:d[0-9]+]], d0
27-
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
28-
; CHECK-NEXT: sxtw x0, [[WREG]]
29-
; CHECK-NEXT: ret
3034
define i64 @testmsxd(double %x) {
35+
; CHECK-LABEL: testmsxd:
36+
; CHECK: // %bb.0: // %entry
37+
; CHECK-NEXT: frintx d0, d0
38+
; CHECK-NEXT: fcvtzs w8, d0
39+
; CHECK-NEXT: sxtw x0, w8
40+
; CHECK-NEXT: ret
3141
entry:
3242
%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
3343
%conv = sext i32 %0 to i64
3444
ret i64 %conv
3545
}
3646

37-
; CHECK-LABEL: testmswd:
38-
; CHECK: frintx [[DREG:d[0-9]+]], d0
39-
; CHECK-NEXT: fcvtzs [[WREG:w[0-9]+]], [[DREG]]
40-
; CHECK-NEXT: ret
4147
define i32 @testmswd(double %x) {
48+
; CHECK-LABEL: testmswd:
49+
; CHECK: // %bb.0: // %entry
50+
; CHECK-NEXT: frintx d0, d0
51+
; CHECK-NEXT: fcvtzs w0, d0
52+
; CHECK-NEXT: ret
4253
entry:
4354
%0 = tail call i32 @llvm.lrint.i32.f64(double %x)
4455
ret i32 %0
4556
}
46-
47-
declare i32 @llvm.lrint.i32.f32(float) nounwind readnone
48-
declare i32 @llvm.lrint.i32.f64(double) nounwind readnone
57+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
58+
; CHECK-GI: {{.*}}
59+
; CHECK-SD: {{.*}}

‎llvm/test/CodeGen/AArch64/lround-conv-fp16-win.ll‎

Lines changed: 42 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,33 +1,62 @@
1-
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+fullfp16 | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
24

3-
; CHECK-LABEL: testmhhs:
4-
; CHECK: fcvtas w0, h0
5-
; CHECK: ret
65
define i16 @testmhhs(half %x) {
6+
; CHECK-SD-LABEL: testmhhs:
7+
; CHECK-SD: // %bb.0: // %entry
8+
; CHECK-SD-NEXT: fcvt s0, h0
9+
; CHECK-SD-NEXT: fcvtas w0, s0
10+
; CHECK-SD-NEXT: ret
11+
;
12+
; CHECK-GI-LABEL: testmhhs:
13+
; CHECK-GI: // %bb.0: // %entry
14+
; CHECK-GI-NEXT: fcvt s0, h0
15+
; CHECK-GI-NEXT: fcvtas x0, s0
16+
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
17+
; CHECK-GI-NEXT: ret
718
entry:
819
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
920
%conv = trunc i32 %0 to i16
1021
ret i16 %conv
1122
}
1223

13-
; CHECK-LABEL: testmhws:
14-
; CHECK: fcvtas w0, h0
15-
; CHECK: ret
1624
define i32 @testmhws(half %x) {
25+
; CHECK-SD-LABEL: testmhws:
26+
; CHECK-SD: // %bb.0: // %entry
27+
; CHECK-SD-NEXT: fcvt s0, h0
28+
; CHECK-SD-NEXT: fcvtas w0, s0
29+
; CHECK-SD-NEXT: ret
30+
;
31+
; CHECK-GI-LABEL: testmhws:
32+
; CHECK-GI: // %bb.0: // %entry
33+
; CHECK-GI-NEXT: fcvt s0, h0
34+
; CHECK-GI-NEXT: fcvtas x0, s0
35+
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
36+
; CHECK-GI-NEXT: ret
1737
entry:
1838
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
1939
ret i32 %0
2040
}
2141

22-
; CHECK-LABEL: testmhxs:
23-
; CHECK: fcvtas w8, h0
24-
; CHECK-NEXT: sxtw x0, w8
25-
; CHECK-NEXT: ret
2642
define i64 @testmhxs(half %x) {
43+
; CHECK-SD-LABEL: testmhxs:
44+
; CHECK-SD: // %bb.0: // %entry
45+
; CHECK-SD-NEXT: fcvt s0, h0
46+
; CHECK-SD-NEXT: fcvtas w8, s0
47+
; CHECK-SD-NEXT: sxtw x0, w8
48+
; CHECK-SD-NEXT: ret
49+
;
50+
; CHECK-GI-LABEL: testmhxs:
51+
; CHECK-GI: // %bb.0: // %entry
52+
; CHECK-GI-NEXT: fcvt s0, h0
53+
; CHECK-GI-NEXT: fcvtas x8, s0
54+
; CHECK-GI-NEXT: sxtw x0, w8
55+
; CHECK-GI-NEXT: ret
2756
entry:
2857
%0 = tail call i32 @llvm.lround.i32.f16(half %x)
2958
%conv = sext i32 %0 to i64
3059
ret i64 %conv
3160
}
32-
33-
declare i32 @llvm.lround.i32.f16(half) nounwind readnone
61+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
62+
; CHECK: {{.*}}

‎llvm/test/CodeGen/AArch64/lround-conv-win.ll‎

Lines changed: 47 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,44 +1,74 @@
1-
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
24

3-
; CHECK-LABEL: testmsxs:
4-
; CHECK: fcvtas w8, s0
5-
; CHECK-NEXT: sxtw x0, w8
6-
; CHECK-NEXT: ret
75
define i64 @testmsxs(float %x) {
6+
; CHECK-SD-LABEL: testmsxs:
7+
; CHECK-SD: // %bb.0: // %entry
8+
; CHECK-SD-NEXT: fcvtas w8, s0
9+
; CHECK-SD-NEXT: sxtw x0, w8
10+
; CHECK-SD-NEXT: ret
11+
;
12+
; CHECK-GI-LABEL: testmsxs:
13+
; CHECK-GI: // %bb.0: // %entry
14+
; CHECK-GI-NEXT: fcvtas x8, s0
15+
; CHECK-GI-NEXT: sxtw x0, w8
16+
; CHECK-GI-NEXT: ret
817
entry:
918
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
1019
%conv = sext i32 %0 to i64
1120
ret i64 %conv
1221
}
1322

14-
; CHECK-LABEL: testmsws:
15-
; CHECK: fcvtas w0, s0
16-
; CHECK-NEXT: ret
1723
define i32 @testmsws(float %x) {
24+
; CHECK-SD-LABEL: testmsws:
25+
; CHECK-SD: // %bb.0: // %entry
26+
; CHECK-SD-NEXT: fcvtas w0, s0
27+
; CHECK-SD-NEXT: ret
28+
;
29+
; CHECK-GI-LABEL: testmsws:
30+
; CHECK-GI: // %bb.0: // %entry
31+
; CHECK-GI-NEXT: fcvtas x0, s0
32+
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
33+
; CHECK-GI-NEXT: ret
1834
entry:
1935
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
2036
ret i32 %0
2137
}
2238

23-
; CHECK-LABEL: testmsxd:
24-
; CHECK: fcvtas w8, d0
25-
; CHECK-NEXT: sxtw x0, w8
26-
; CHECK-NEXT: ret
2739
define i64 @testmsxd(double %x) {
40+
; CHECK-SD-LABEL: testmsxd:
41+
; CHECK-SD: // %bb.0: // %entry
42+
; CHECK-SD-NEXT: fcvtas w8, d0
43+
; CHECK-SD-NEXT: sxtw x0, w8
44+
; CHECK-SD-NEXT: ret
45+
;
46+
; CHECK-GI-LABEL: testmsxd:
47+
; CHECK-GI: // %bb.0: // %entry
48+
; CHECK-GI-NEXT: fcvtas x8, d0
49+
; CHECK-GI-NEXT: sxtw x0, w8
50+
; CHECK-GI-NEXT: ret
2851
entry:
2952
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
3053
%conv = sext i32 %0 to i64
3154
ret i64 %conv
3255
}
3356

34-
; CHECK-LABEL: testmswd:
35-
; CHECK: fcvtas w0, d0
36-
; CHECK-NEXT: ret
3757
define i32 @testmswd(double %x) {
58+
; CHECK-SD-LABEL: testmswd:
59+
; CHECK-SD: // %bb.0: // %entry
60+
; CHECK-SD-NEXT: fcvtas w0, d0
61+
; CHECK-SD-NEXT: ret
62+
;
63+
; CHECK-GI-LABEL: testmswd:
64+
; CHECK-GI: // %bb.0: // %entry
65+
; CHECK-GI-NEXT: fcvtas x0, d0
66+
; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
67+
; CHECK-GI-NEXT: ret
3868
entry:
3969
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
4070
ret i32 %0
4171
}
4272

43-
declare i32 @llvm.lround.i32.f32(float) nounwind readnone
44-
declare i32 @llvm.lround.i32.f64(double) nounwind readnone
73+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
74+
; CHECK: {{.*}}

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