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[RISCV] Support Load/Store Global assembler pseudos for Zilsd. (#134950)
This adds support for 'ld \<rd\> \<symbol\>' and 'sd \<rd\>, \<symbol\>, \<rt\>' to match what we do for RV32. I've changed the interface to emitAuipcInstPair to use MCRegister instead of MCOperand since we need to convert a GPRPair to GPR for TmpReg for the load case.
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 25 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -135,7 +135,7 @@ class RISCVAsmParser : public MCTargetAsmParser {
135135

136136
// Helper to emit a combination of AUIPC and SecondOpcode. Used to implement
137137
// helpers such as emitLoadLocalAddress and emitLoadAddress.
138-
void emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
138+
void emitAuipcInstPair(MCRegister DestReg, MCRegister TmpReg,
139139
const MCExpr *Symbol, RISCVMCExpr::Specifier VKHi,
140140
unsigned SecondOpcode, SMLoc IDLoc, MCStreamer &Out);
141141

@@ -3302,7 +3302,7 @@ void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
33023302
}
33033303
}
33043304

3305-
void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
3305+
void RISCVAsmParser::emitAuipcInstPair(MCRegister DestReg, MCRegister TmpReg,
33063306
const MCExpr *Symbol,
33073307
RISCVMCExpr::Specifier VKHi,
33083308
unsigned SecondOpcode, SMLoc IDLoc,
@@ -3316,15 +3316,15 @@ void RISCVAsmParser::emitAuipcInstPair(MCOperand DestReg, MCOperand TmpReg,
33163316
Out.emitLabel(TmpLabel);
33173317

33183318
const RISCVMCExpr *SymbolHi = RISCVMCExpr::create(Symbol, VKHi, Ctx);
3319-
emitToStreamer(
3320-
Out, MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolHi));
3319+
emitToStreamer(Out,
3320+
MCInstBuilder(RISCV::AUIPC).addReg(TmpReg).addExpr(SymbolHi));
33213321

33223322
const MCExpr *RefToLinkTmpLabel = RISCVMCExpr::create(
33233323
MCSymbolRefExpr::create(TmpLabel, Ctx), RISCVMCExpr::VK_PCREL_LO, Ctx);
33243324

33253325
emitToStreamer(Out, MCInstBuilder(SecondOpcode)
3326-
.addOperand(DestReg)
3327-
.addOperand(TmpReg)
3326+
.addReg(DestReg)
3327+
.addReg(TmpReg)
33283328
.addExpr(RefToLinkTmpLabel));
33293329
}
33303330

@@ -3336,7 +3336,7 @@ void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
33363336
// expands to
33373337
// TmpLabel: AUIPC rdest, %pcrel_hi(symbol)
33383338
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
3339-
MCOperand DestReg = Inst.getOperand(0);
3339+
MCRegister DestReg = Inst.getOperand(0).getReg();
33403340
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
33413341
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_PCREL_HI,
33423342
RISCV::ADDI, IDLoc, Out);
@@ -3350,7 +3350,7 @@ void RISCVAsmParser::emitLoadGlobalAddress(MCInst &Inst, SMLoc IDLoc,
33503350
// expands to
33513351
// TmpLabel: AUIPC rdest, %got_pcrel_hi(symbol)
33523352
// Lx rdest, %pcrel_lo(TmpLabel)(rdest)
3353-
MCOperand DestReg = Inst.getOperand(0);
3353+
MCRegister DestReg = Inst.getOperand(0).getReg();
33543354
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
33553355
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
33563356
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_GOT_HI,
@@ -3380,7 +3380,7 @@ void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
33803380
// expands to
33813381
// TmpLabel: AUIPC rdest, %tls_ie_pcrel_hi(symbol)
33823382
// Lx rdest, %pcrel_lo(TmpLabel)(rdest)
3383-
MCOperand DestReg = Inst.getOperand(0);
3383+
MCRegister DestReg = Inst.getOperand(0).getReg();
33843384
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
33853385
unsigned SecondOpcode = isRV64() ? RISCV::LD : RISCV::LW;
33863386
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GOT_HI,
@@ -3395,7 +3395,7 @@ void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
33953395
// expands to
33963396
// TmpLabel: AUIPC rdest, %tls_gd_pcrel_hi(symbol)
33973397
// ADDI rdest, rdest, %pcrel_lo(TmpLabel)
3398-
MCOperand DestReg = Inst.getOperand(0);
3398+
MCRegister DestReg = Inst.getOperand(0).getReg();
33993399
const MCExpr *Symbol = Inst.getOperand(1).getExpr();
34003400
emitAuipcInstPair(DestReg, DestReg, Symbol, RISCVMCExpr::VK_TLS_GD_HI,
34013401
RISCV::ADDI, IDLoc, Out);
@@ -3412,9 +3412,16 @@ void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
34123412
// TmpLabel: AUIPC tmp, %pcrel_hi(symbol)
34133413
// [S|L]X rd, %pcrel_lo(TmpLabel)(tmp)
34143414
unsigned DestRegOpIdx = HasTmpReg ? 1 : 0;
3415-
MCOperand DestReg = Inst.getOperand(DestRegOpIdx);
3415+
MCRegister DestReg = Inst.getOperand(DestRegOpIdx).getReg();
34163416
unsigned SymbolOpIdx = HasTmpReg ? 2 : 1;
3417-
MCOperand TmpReg = Inst.getOperand(0);
3417+
MCRegister TmpReg = Inst.getOperand(0).getReg();
3418+
3419+
// If TmpReg is a GPR pair, get the even register.
3420+
if (RISCVMCRegisterClasses[RISCV::GPRPairRegClassID].contains(TmpReg)) {
3421+
const MCRegisterInfo *RI = getContext().getRegisterInfo();
3422+
TmpReg = RI->getSubReg(TmpReg, RISCV::sub_gpr_even);
3423+
}
3424+
34183425
const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr();
34193426
emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_PCREL_HI, Opcode,
34203427
IDLoc, Out);
@@ -3771,6 +3778,9 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
37713778
case RISCV::PseudoLD:
37723779
emitLoadStoreSymbol(Inst, RISCV::LD, IDLoc, Out, /*HasTmpReg=*/false);
37733780
return false;
3781+
case RISCV::PseudoLD_RV32:
3782+
emitLoadStoreSymbol(Inst, RISCV::LD_RV32, IDLoc, Out, /*HasTmpReg=*/false);
3783+
return false;
37743784
case RISCV::PseudoFLH:
37753785
emitLoadStoreSymbol(Inst, RISCV::FLH, IDLoc, Out, /*HasTmpReg=*/true);
37763786
return false;
@@ -3795,6 +3805,9 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
37953805
case RISCV::PseudoSD:
37963806
emitLoadStoreSymbol(Inst, RISCV::SD, IDLoc, Out, /*HasTmpReg=*/true);
37973807
return false;
3808+
case RISCV::PseudoSD_RV32:
3809+
emitLoadStoreSymbol(Inst, RISCV::SD_RV32, IDLoc, Out, /*HasTmpReg=*/true);
3810+
return false;
37983811
case RISCV::PseudoFSH:
37993812
emitLoadStoreSymbol(Inst, RISCV::FSH, IDLoc, Out, /*HasTmpReg=*/true);
38003813
return false;

‎llvm/lib/Target/RISCV/RISCVInstrFormats.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -301,8 +301,8 @@ class PseudoQuietFCMP<DAGOperand Ty>
301301
}
302302

303303
// Pseudo load instructions.
304-
class PseudoLoad<string opcodestr>
305-
: Pseudo<(outs GPR:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
304+
class PseudoLoad<string opcodestr, DAGOperand rdty = GPR>
305+
: Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
306306
let hasSideEffects = 0;
307307
let mayLoad = 1;
308308
let mayStore = 0;
@@ -320,7 +320,7 @@ class PseudoFloatLoad<string opcodestr, RegisterClass rdty>
320320
}
321321

322322
// Pseudo store instructions.
323-
class PseudoStore<string opcodestr, RegisterClass rsty = GPR>
323+
class PseudoStore<string opcodestr, DAGOperand rsty = GPR>
324324
: Pseudo<(outs GPR:$tmp), (ins rsty:$rs, bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
325325
let hasSideEffects = 0;
326326
let mayLoad = 0;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZilsd.td‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,9 @@ def SD_RV32 : Store_rri<0b011, "sd", GPRPairRV32>,
3030
//===----------------------------------------------------------------------===//
3131

3232
let Predicates = [HasStdExtZilsd, IsRV32] in {
33+
def PseudoLD_RV32 : PseudoLoad<"ld", GPRPairRV32>;
34+
def PseudoSD_RV32 : PseudoStore<"sd", GPRPairRV32>;
35+
3336
def : InstAlias<"ld $rd, (${rs1})", (LD_RV32 GPRPairRV32:$rd, GPR:$rs1, 0), 0>;
3437
def : InstAlias<"sd $rs2, (${rs1})", (SD_RV32 GPRPairRV32:$rs2, GPR:$rs1, 0), 0>;
3538
}

‎llvm/test/MC/RISCV/rv32zilsd-pseudos.s‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
# RUN: llvm-mc %s -triple=riscv32 -mattr=+zilsd | FileCheck %s
2+
3+
# CHECK: .Lpcrel_hi0:
4+
# CHECK: auipc a4, %pcrel_hi(a_symbol)
5+
# CHECK: ld a4, %pcrel_lo(.Lpcrel_hi0)(a4)
6+
ld a4, a_symbol
7+
8+
# CHECK: .Lpcrel_hi1:
9+
# CHECK: auipc a3, %pcrel_hi(a_symbol)
10+
# CHECK: sd a6, %pcrel_lo(.Lpcrel_hi1)(a3)
11+
sd a6, a_symbol, a3

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