|
| 1 | +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +// RUN: %clang_cc1 -std=c++20 -triple=x86_64-linux-gnu -emit-llvm -o - %s | FileCheck %s |
| 3 | + |
| 4 | + |
| 5 | +template <unsigned Size> |
| 6 | +struct S { |
| 7 | + char data[Size]; |
| 8 | +}; |
| 9 | + |
| 10 | +// CHECK-LABEL: define dso_local noundef zeroext i1 @_Z21test_compare_exchangePU7_Atomic1SILj3EEPS0_S0_( |
| 11 | +// CHECK-SAME: ptr noundef [[A:%.*]], ptr noundef [[EXPECTED:%.*]], i24 [[DESIRED_COERCE:%.*]]) #[[ATTR0:[0-9]+]] { |
| 12 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 13 | +// CHECK-NEXT: [[DESIRED:%.*]] = alloca [[STRUCT_S:%.*]], align 1 |
| 14 | +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| 15 | +// CHECK-NEXT: [[EXPECTED_ADDR:%.*]] = alloca ptr, align 8 |
| 16 | +// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca [[STRUCT_S]], align 1 |
| 17 | +// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca { [[STRUCT_S]], [1 x i8] }, align 4 |
| 18 | +// CHECK-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca { [[STRUCT_S]], [1 x i8] }, align 4 |
| 19 | +// CHECK-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1 |
| 20 | +// CHECK-NEXT: [[OLD_TMP:%.*]] = alloca i32, align 4 |
| 21 | +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_S]], ptr [[DESIRED]], i32 0, i32 0 |
| 22 | +// CHECK-NEXT: store i24 [[DESIRED_COERCE]], ptr [[COERCE_DIVE]], align 1 |
| 23 | +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| 24 | +// CHECK-NEXT: store ptr [[EXPECTED]], ptr [[EXPECTED_ADDR]], align 8 |
| 25 | +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| 26 | +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[EXPECTED_ADDR]], align 8 |
| 27 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTATOMICTMP]], ptr align 1 [[DESIRED]], i64 3, i1 false) |
| 28 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ATOMIC_TEMP]], ptr align 1 [[TMP1]], i64 3, i1 false) |
| 29 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ATOMIC_TEMP1]], ptr align 1 [[DOTATOMICTMP]], i64 3, i1 false) |
| 30 | +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ATOMIC_TEMP]], align 4 |
| 31 | +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ATOMIC_TEMP1]], align 4 |
| 32 | +// CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[TMP0]], i32 [[TMP2]], i32 [[TMP3]] monotonic monotonic, align 4 |
| 33 | +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, i1 } [[TMP4]], 0 |
| 34 | +// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 |
| 35 | +// CHECK-NEXT: br i1 [[TMP6]], label %[[CMPXCHG_CONTINUE:.*]], label %[[CMPXCHG_STORE_EXPECTED:.*]] |
| 36 | +// CHECK: [[CMPXCHG_STORE_EXPECTED]]: |
| 37 | +// CHECK-NEXT: store i32 [[TMP5]], ptr [[OLD_TMP]], align 4 |
| 38 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP1]], ptr align 4 [[OLD_TMP]], i64 3, i1 false) |
| 39 | +// CHECK-NEXT: br label %[[CMPXCHG_CONTINUE]] |
| 40 | +// CHECK: [[CMPXCHG_CONTINUE]]: |
| 41 | +// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP6]] to i8 |
| 42 | +// CHECK-NEXT: store i8 [[STOREDV]], ptr [[CMPXCHG_BOOL]], align 1 |
| 43 | +// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[CMPXCHG_BOOL]], align 1 |
| 44 | +// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 |
| 45 | +// CHECK-NEXT: ret i1 [[LOADEDV]] |
| 46 | +// |
| 47 | +bool test_compare_exchange(_Atomic(S<3>)* a, S<3>* expected, S<3> desired) { |
| 48 | + return __c11_atomic_compare_exchange_strong(a, expected, desired, 0, 0); |
| 49 | +} |
| 50 | + |
| 51 | + |
| 52 | +// CHECK-LABEL: define dso_local noundef zeroext i1 @_Z21test_compare_exchangePU7_Atomic1SILj4EEPS0_S0_( |
| 53 | +// CHECK-SAME: ptr noundef [[A:%.*]], ptr noundef [[EXPECTED:%.*]], i32 [[DESIRED_COERCE:%.*]]) #[[ATTR0]] { |
| 54 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 55 | +// CHECK-NEXT: [[DESIRED:%.*]] = alloca [[STRUCT_S_0:%.*]], align 1 |
| 56 | +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| 57 | +// CHECK-NEXT: [[EXPECTED_ADDR:%.*]] = alloca ptr, align 8 |
| 58 | +// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca [[STRUCT_S_0]], align 1 |
| 59 | +// CHECK-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1 |
| 60 | +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_S_0]], ptr [[DESIRED]], i32 0, i32 0 |
| 61 | +// CHECK-NEXT: store i32 [[DESIRED_COERCE]], ptr [[COERCE_DIVE]], align 1 |
| 62 | +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| 63 | +// CHECK-NEXT: store ptr [[EXPECTED]], ptr [[EXPECTED_ADDR]], align 8 |
| 64 | +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| 65 | +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[EXPECTED_ADDR]], align 8 |
| 66 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTATOMICTMP]], ptr align 1 [[DESIRED]], i64 4, i1 false) |
| 67 | +// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 1 |
| 68 | +// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTATOMICTMP]], align 1 |
| 69 | +// CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[TMP0]], i32 [[TMP2]], i32 [[TMP3]] monotonic monotonic, align 4 |
| 70 | +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i32, i1 } [[TMP4]], 0 |
| 71 | +// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i32, i1 } [[TMP4]], 1 |
| 72 | +// CHECK-NEXT: br i1 [[TMP6]], label %[[CMPXCHG_CONTINUE:.*]], label %[[CMPXCHG_STORE_EXPECTED:.*]] |
| 73 | +// CHECK: [[CMPXCHG_STORE_EXPECTED]]: |
| 74 | +// CHECK-NEXT: store i32 [[TMP5]], ptr [[TMP1]], align 1 |
| 75 | +// CHECK-NEXT: br label %[[CMPXCHG_CONTINUE]] |
| 76 | +// CHECK: [[CMPXCHG_CONTINUE]]: |
| 77 | +// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP6]] to i8 |
| 78 | +// CHECK-NEXT: store i8 [[STOREDV]], ptr [[CMPXCHG_BOOL]], align 1 |
| 79 | +// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[CMPXCHG_BOOL]], align 1 |
| 80 | +// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 |
| 81 | +// CHECK-NEXT: ret i1 [[LOADEDV]] |
| 82 | +// |
| 83 | +bool test_compare_exchange(_Atomic(S<4>)* a, S<4>* expected, S<4> desired) { |
| 84 | + return __c11_atomic_compare_exchange_strong(a, expected, desired, 0, 0); |
| 85 | +} |
| 86 | + |
| 87 | +// CHECK-LABEL: define dso_local noundef zeroext i1 @_Z21test_compare_exchangePU7_Atomic1SILj6EEPS0_S0_( |
| 88 | +// CHECK-SAME: ptr noundef [[A:%.*]], ptr noundef [[EXPECTED:%.*]], i48 [[DESIRED_COERCE:%.*]]) #[[ATTR0]] { |
| 89 | +// CHECK-NEXT: [[ENTRY:.*:]] |
| 90 | +// CHECK-NEXT: [[DESIRED:%.*]] = alloca [[STRUCT_S_1:%.*]], align 1 |
| 91 | +// CHECK-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8 |
| 92 | +// CHECK-NEXT: [[EXPECTED_ADDR:%.*]] = alloca ptr, align 8 |
| 93 | +// CHECK-NEXT: [[DOTATOMICTMP:%.*]] = alloca [[STRUCT_S_1]], align 1 |
| 94 | +// CHECK-NEXT: [[ATOMIC_TEMP:%.*]] = alloca { [[STRUCT_S_1]], [2 x i8] }, align 8 |
| 95 | +// CHECK-NEXT: [[ATOMIC_TEMP1:%.*]] = alloca { [[STRUCT_S_1]], [2 x i8] }, align 8 |
| 96 | +// CHECK-NEXT: [[CMPXCHG_BOOL:%.*]] = alloca i8, align 1 |
| 97 | +// CHECK-NEXT: [[OLD_TMP:%.*]] = alloca i64, align 8 |
| 98 | +// CHECK-NEXT: [[COERCE_DIVE:%.*]] = getelementptr inbounds nuw [[STRUCT_S_1]], ptr [[DESIRED]], i32 0, i32 0 |
| 99 | +// CHECK-NEXT: store i48 [[DESIRED_COERCE]], ptr [[COERCE_DIVE]], align 1 |
| 100 | +// CHECK-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8 |
| 101 | +// CHECK-NEXT: store ptr [[EXPECTED]], ptr [[EXPECTED_ADDR]], align 8 |
| 102 | +// CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8 |
| 103 | +// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[EXPECTED_ADDR]], align 8 |
| 104 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[DOTATOMICTMP]], ptr align 1 [[DESIRED]], i64 6, i1 false) |
| 105 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[ATOMIC_TEMP]], ptr align 1 [[TMP1]], i64 6, i1 false) |
| 106 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[ATOMIC_TEMP1]], ptr align 1 [[DOTATOMICTMP]], i64 6, i1 false) |
| 107 | +// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ATOMIC_TEMP]], align 8 |
| 108 | +// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[ATOMIC_TEMP1]], align 8 |
| 109 | +// CHECK-NEXT: [[TMP4:%.*]] = cmpxchg ptr [[TMP0]], i64 [[TMP2]], i64 [[TMP3]] monotonic monotonic, align 8 |
| 110 | +// CHECK-NEXT: [[TMP5:%.*]] = extractvalue { i64, i1 } [[TMP4]], 0 |
| 111 | +// CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i64, i1 } [[TMP4]], 1 |
| 112 | +// CHECK-NEXT: br i1 [[TMP6]], label %[[CMPXCHG_CONTINUE:.*]], label %[[CMPXCHG_STORE_EXPECTED:.*]] |
| 113 | +// CHECK: [[CMPXCHG_STORE_EXPECTED]]: |
| 114 | +// CHECK-NEXT: store i64 [[TMP5]], ptr [[OLD_TMP]], align 8 |
| 115 | +// CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[TMP1]], ptr align 8 [[OLD_TMP]], i64 6, i1 false) |
| 116 | +// CHECK-NEXT: br label %[[CMPXCHG_CONTINUE]] |
| 117 | +// CHECK: [[CMPXCHG_CONTINUE]]: |
| 118 | +// CHECK-NEXT: [[STOREDV:%.*]] = zext i1 [[TMP6]] to i8 |
| 119 | +// CHECK-NEXT: store i8 [[STOREDV]], ptr [[CMPXCHG_BOOL]], align 1 |
| 120 | +// CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[CMPXCHG_BOOL]], align 1 |
| 121 | +// CHECK-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP7]] to i1 |
| 122 | +// CHECK-NEXT: ret i1 [[LOADEDV]] |
| 123 | +// |
| 124 | +bool test_compare_exchange(_Atomic(S<6>)* a, S<6>* expected, S<6> desired) { |
| 125 | + return __c11_atomic_compare_exchange_strong(a, expected, desired, 0, 0); |
| 126 | +} |
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