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Always store a carry bit in a GPR
1 parent b9517ee commit 5ca565c

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5 files changed

+42
-36
lines changed

5 files changed

+42
-36
lines changed

‎llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp‎

Lines changed: 6 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1226,9 +1226,10 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
12261226
Def->getOpcode() == TargetOpcode::G_USUBE ||
12271227
Def->getOpcode() == TargetOpcode::G_USUBO) {
12281228
// carry set by prev ADD/SUB.
1229-
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY),
1230-
X86::EFLAGS)
1231-
.addReg(CarryInReg);
1229+
1230+
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::CMP8ri))
1231+
.addReg(CarryInReg)
1232+
.addImm(1);
12321233

12331234
if (!RBI.constrainGenericRegister(CarryInReg, *CarryRC, MRI))
12341235
return false;
@@ -1249,32 +1250,13 @@ bool X86InstructionSelector::selectUAddSub(MachineInstr &I,
12491250
.addReg(Op0Reg)
12501251
.addReg(Op1Reg);
12511252

1252-
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1253-
.addReg(X86::EFLAGS);
1253+
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr),
1254+
CarryOutReg).addImm(X86::COND_B);
12541255

12551256
if (!constrainSelectedInstRegOperands(Inst, TII, TRI, RBI) ||
12561257
!RBI.constrainGenericRegister(CarryOutReg, *CarryRC, MRI))
12571258
return false;
12581259

1259-
// If there are instructions that use carry as value, we need to lower it
1260-
// differently than setting EFLAGS
1261-
Register SetCarryCC;
1262-
for (auto &Use :
1263-
llvm::make_early_inc_range(MRI.use_nodbg_operands(CarryOutReg))) {
1264-
MachineInstr *MI = Use.getParent();
1265-
if (MI->isCopy() && MI->getOperand(0).getReg() == X86::EFLAGS)
1266-
continue;
1267-
if (!SetCarryCC) {
1268-
SetCarryCC = MRI.createGenericVirtualRegister(MRI.getType(CarryOutReg));
1269-
BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr),
1270-
SetCarryCC)
1271-
.addImm(X86::COND_B);
1272-
if (!RBI.constrainGenericRegister(SetCarryCC, *CarryRC, MRI))
1273-
return false;
1274-
}
1275-
Use.setReg(SetCarryCC);
1276-
}
1277-
12781260
I.eraseFromParent();
12791261
return true;
12801262
}

‎llvm/test/CodeGen/X86/GlobalISel/add-scalar.ll‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,15 @@ define i128 @test_add_i128(i128 %arg1, i128 %arg2) nounwind {
77
; X64: # %bb.0:
88
; X64-NEXT: movq %rdx, %rax
99
; X64-NEXT: addq %rdi, %rax
10+
; X64-NEXT: setb %dl
11+
; X64-NEXT: cmpb $1, %dl
1012
; X64-NEXT: adcq %rsi, %rcx
1113
; X64-NEXT: movq %rcx, %rdx
1214
; X64-NEXT: retq
1315
;
1416
; X86-LABEL: test_add_i128:
1517
; X86: # %bb.0:
18+
; X86-NEXT: pushl %ebx
1619
; X86-NEXT: pushl %edi
1720
; X86-NEXT: pushl %esi
1821
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -21,15 +24,22 @@ define i128 @test_add_i128(i128 %arg1, i128 %arg2) nounwind {
2124
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
2225
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
2326
; X86-NEXT: addl {{[0-9]+}}(%esp), %ecx
27+
; X86-NEXT: setb %bl
28+
; X86-NEXT: cmpb $1, %bl
2429
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
30+
; X86-NEXT: setb %bl
31+
; X86-NEXT: cmpb $1, %bl
2532
; X86-NEXT: adcl {{[0-9]+}}(%esp), %esi
33+
; X86-NEXT: setb %bl
34+
; X86-NEXT: cmpb $1, %bl
2635
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edi
2736
; X86-NEXT: movl %ecx, (%eax)
2837
; X86-NEXT: movl %edx, 4(%eax)
2938
; X86-NEXT: movl %esi, 8(%eax)
3039
; X86-NEXT: movl %edi, 12(%eax)
3140
; X86-NEXT: popl %esi
3241
; X86-NEXT: popl %edi
42+
; X86-NEXT: popl %ebx
3343
; X86-NEXT: retl
3444
%ret = add i128 %arg1, %arg2
3545
ret i128 %ret
@@ -46,6 +56,8 @@ define i64 @test_add_i64(i64 %arg1, i64 %arg2) {
4656
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
4757
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
4858
; X86-NEXT: addl {{[0-9]+}}(%esp), %eax
59+
; X86-NEXT: setb %cl
60+
; X86-NEXT: cmpb $1, %cl
4961
; X86-NEXT: adcl {{[0-9]+}}(%esp), %edx
5062
; X86-NEXT: retl
5163
%ret = add i64 %arg1, %arg2

‎llvm/test/CodeGen/X86/GlobalISel/pr49087.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2-
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -global-isel < %s 2>&1 | FileCheck %s
2+
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -o - -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s
33

44
define i32 @test_01(ptr %p, i64 %len, i32 %x) {
55
; CHECK-LABEL: test_01:

‎llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -27,17 +27,17 @@ body: |
2727
bb.0 (%ir-block.0):
2828
; X32-LABEL: name: test_add_i64
2929
; X32: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
30-
; X32: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
31-
; X32: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
32-
; X32: [[DEF3:%[0-9]+]]:gr32 = IMPLICIT_DEF
33-
; X32: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[DEF]], [[DEF2]], implicit-def $eflags
34-
; X32: [[COPY:%[0-9]+]]:gr8 = COPY $eflags
35-
; X32: $eflags = COPY [[COPY]]
36-
; X32: [[ADC32rr:%[0-9]+]]:gr32 = ADC32rr [[DEF1]], [[DEF3]], implicit-def $eflags, implicit $eflags
37-
; X32: [[COPY1:%[0-9]+]]:gr8 = COPY $eflags
38-
; X32: $eax = COPY [[ADD32rr]]
39-
; X32: $edx = COPY [[ADC32rr]]
40-
; X32: RET 0, implicit $eax, implicit $edx
30+
; X32-NEXT: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
31+
; X32-NEXT: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
32+
; X32-NEXT: [[DEF3:%[0-9]+]]:gr32 = IMPLICIT_DEF
33+
; X32-NEXT: [[ADD32rr:%[0-9]+]]:gr32 = ADD32rr [[DEF]], [[DEF2]], implicit-def $eflags
34+
; X32-NEXT: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
35+
; X32-NEXT: CMP8ri [[SETCCr]], 1, implicit-def $eflags
36+
; X32-NEXT: [[ADC32rr:%[0-9]+]]:gr32 = ADC32rr [[DEF1]], [[DEF3]], implicit-def $eflags, implicit $eflags
37+
; X32-NEXT: [[SETCCr1:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
38+
; X32-NEXT: $eax = COPY [[ADD32rr]]
39+
; X32-NEXT: $edx = COPY [[ADC32rr]]
40+
; X32-NEXT: RET 0, implicit $eax, implicit $edx
4141
%0(s32) = IMPLICIT_DEF
4242
%1(s32) = IMPLICIT_DEF
4343
%2(s32) = IMPLICIT_DEF

‎llvm/test/CodeGen/X86/GlobalISel/sub-scalar.ll‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,15 @@ define i128 @test_sub_i128(i128 %arg1, i128 %arg2) nounwind {
77
; X64: # %bb.0:
88
; X64-NEXT: movq %rdi, %rax
99
; X64-NEXT: subq %rdx, %rax
10+
; X64-NEXT: setb %dl
11+
; X64-NEXT: cmpb $1, %dl
1012
; X64-NEXT: sbbq %rcx, %rsi
1113
; X64-NEXT: movq %rsi, %rdx
1214
; X64-NEXT: retq
1315
;
1416
; X86-LABEL: test_sub_i128:
1517
; X86: # %bb.0:
18+
; X86-NEXT: pushl %ebx
1619
; X86-NEXT: pushl %edi
1720
; X86-NEXT: pushl %esi
1821
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
@@ -21,15 +24,22 @@ define i128 @test_sub_i128(i128 %arg1, i128 %arg2) nounwind {
2124
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
2225
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
2326
; X86-NEXT: subl {{[0-9]+}}(%esp), %ecx
27+
; X86-NEXT: setb %bl
28+
; X86-NEXT: cmpb $1, %bl
2429
; X86-NEXT: sbbl {{[0-9]+}}(%esp), %edx
30+
; X86-NEXT: setb %bl
31+
; X86-NEXT: cmpb $1, %bl
2532
; X86-NEXT: sbbl {{[0-9]+}}(%esp), %esi
33+
; X86-NEXT: setb %bl
34+
; X86-NEXT: cmpb $1, %bl
2635
; X86-NEXT: sbbl {{[0-9]+}}(%esp), %edi
2736
; X86-NEXT: movl %ecx, (%eax)
2837
; X86-NEXT: movl %edx, 4(%eax)
2938
; X86-NEXT: movl %esi, 8(%eax)
3039
; X86-NEXT: movl %edi, 12(%eax)
3140
; X86-NEXT: popl %esi
3241
; X86-NEXT: popl %edi
42+
; X86-NEXT: popl %ebx
3343
; X86-NEXT: retl
3444
%ret = sub i128 %arg1, %arg2
3545
ret i128 %ret
@@ -47,6 +57,8 @@ define i64 @test_sub_i64(i64 %arg1, i64 %arg2) {
4757
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
4858
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
4959
; X86-NEXT: subl {{[0-9]+}}(%esp), %eax
60+
; X86-NEXT: setb %cl
61+
; X86-NEXT: cmpb $1, %cl
5062
; X86-NEXT: sbbl {{[0-9]+}}(%esp), %edx
5163
; X86-NEXT: retl
5264
%ret = sub i64 %arg1, %arg2

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