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[RISCV] Simplify usage of SplatPat_simm5_plus1. NFC (#125340)
Make SplatPat_simm5_plus1 responsible for decrementing the immediate instead of requiring DecImm SDNodeXForm to be used after. This allows better sharing of tablegen classes.
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3 files changed

+34
-70
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3538,7 +3538,8 @@ bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
35383538
static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
35393539
SelectionDAG &DAG,
35403540
const RISCVSubtarget &Subtarget,
3541-
std::function<bool(int64_t)> ValidateImm) {
3541+
std::function<bool(int64_t)> ValidateImm,
3542+
bool Decrement = false) {
35423543
SDValue Splat = findVSplat(N);
35433544
if (!Splat || !isa<ConstantSDNode>(Splat.getOperand(1)))
35443545
return false;
@@ -3561,6 +3562,9 @@ static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
35613562
if (!ValidateImm(SplatImm))
35623563
return false;
35633564

3565+
if (Decrement)
3566+
SplatImm -= 1;
3567+
35643568
SplatVal =
35653569
DAG.getSignedTargetConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT());
35663570
return true;
@@ -3574,15 +3578,18 @@ bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
35743578
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
35753579
return selectVSplatImmHelper(
35763580
N, SplatVal, *CurDAG, *Subtarget,
3577-
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; });
3581+
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; },
3582+
/*Decrement=*/true);
35783583
}
35793584

35803585
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,
35813586
SDValue &SplatVal) {
35823587
return selectVSplatImmHelper(
3583-
N, SplatVal, *CurDAG, *Subtarget, [](int64_t Imm) {
3588+
N, SplatVal, *CurDAG, *Subtarget,
3589+
[](int64_t Imm) {
35843590
return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
3585-
});
3591+
},
3592+
/*Decrement=*/true);
35863593
}
35873594

35883595
bool RISCVDAGToDAGISel::selectVSplatUimm(SDValue N, unsigned Bits,

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td‎

Lines changed: 11 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -313,29 +313,10 @@ multiclass VPatIntegerSetCCSDNode_VX_Swappable<string instruction_name,
313313
SplatPat, GPR>;
314314

315315
multiclass VPatIntegerSetCCSDNode_VI_Swappable<string instruction_name,
316-
CondCode cc, CondCode invcc>
316+
CondCode cc, CondCode invcc,
317+
ComplexPattern splatpat_kind = SplatPat_simm5>
317318
: VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VI",
318-
SplatPat_simm5, simm5>;
319-
320-
multiclass VPatIntegerSetCCSDNode_VIPlus1_Swappable<string instruction_name,
321-
CondCode cc, CondCode invcc,
322-
ComplexPattern splatpat_kind> {
323-
foreach vti = AllIntegerVectors in {
324-
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
325-
let Predicates = GetVTypePredicates<vti>.Predicates in {
326-
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
327-
(vti.Vector (splatpat_kind simm5:$rs2)),
328-
cc)),
329-
(instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
330-
vti.AVL, vti.Log2SEW)>;
331-
def : Pat<(vti.Mask (setcc (vti.Vector (splatpat_kind simm5:$rs2)),
332-
(vti.Vector vti.RegClass:$rs1),
333-
invcc)),
334-
(instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
335-
vti.AVL, vti.Log2SEW)>;
336-
}
337-
}
338-
}
319+
splatpat_kind, simm5>;
339320

340321
multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
341322
string inst_name,
@@ -1021,14 +1002,14 @@ defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
10211002
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
10221003
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
10231004

1024-
defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT,
1025-
SplatPat_simm5_plus1>;
1026-
defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
1027-
SplatPat_simm5_plus1_nonzero>;
1028-
defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGT", SETGE, SETLE,
1029-
SplatPat_simm5_plus1>;
1030-
defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
1031-
SplatPat_simm5_plus1_nonzero>;
1005+
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLE", SETLT, SETGT,
1006+
SplatPat_simm5_plus1>;
1007+
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
1008+
SplatPat_simm5_plus1_nonzero>;
1009+
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGE, SETLE,
1010+
SplatPat_simm5_plus1>;
1011+
defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
1012+
SplatPat_simm5_plus1_nonzero>;
10321013

10331014
// 11.9. Vector Integer Min/Max Instructions
10341015
defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 12 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1052,40 +1052,16 @@ multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_nam
10521052
}
10531053

10541054
multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
1055-
CondCode cc, CondCode invcc> {
1056-
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
1057-
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
1058-
(SplatPat_simm5 simm5:$rs2), cc,
1059-
VR:$passthru,
1060-
(vti.Mask V0),
1061-
VLOpFrag)),
1062-
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
1063-
XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
1064-
vti.Log2SEW)>;
1065-
1066-
// FIXME: Can do some canonicalization to remove these patterns.
1067-
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
1068-
(vti.Vector vti.RegClass:$rs1), invcc,
1069-
VR:$passthru,
1070-
(vti.Mask V0),
1071-
VLOpFrag)),
1072-
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
1073-
simm5:$rs2, (vti.Mask V0), GPR:$vl,
1074-
vti.Log2SEW)>;
1075-
}
1076-
1077-
multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
1078-
string instruction_name,
1079-
CondCode cc, CondCode invcc,
1080-
ComplexPattern splatpat_kind> {
1055+
CondCode cc, CondCode invcc,
1056+
ComplexPattern splatpat_kind = SplatPat_simm5> {
10811057
defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK");
10821058
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
10831059
(splatpat_kind simm5:$rs2), cc,
10841060
VR:$passthru,
10851061
(vti.Mask V0),
10861062
VLOpFrag)),
10871063
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
1088-
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
1064+
XLenVT:$rs2, (vti.Mask V0), GPR:$vl,
10891065
vti.Log2SEW)>;
10901066

10911067
// FIXME: Can do some canonicalization to remove these patterns.
@@ -1095,7 +1071,7 @@ multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti,
10951071
(vti.Mask V0),
10961072
VLOpFrag)),
10971073
(instruction_masked VR:$passthru, vti.RegClass:$rs1,
1098-
(DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl,
1074+
simm5:$rs2, (vti.Mask V0), GPR:$vl,
10991075
vti.Log2SEW)>;
11001076
}
11011077

@@ -2173,14 +2149,14 @@ foreach vti = AllIntegerVectors in {
21732149
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
21742150
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
21752151

2176-
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
2177-
SplatPat_simm5_plus1>;
2178-
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
2179-
SplatPat_simm5_plus1_nonzero>;
2180-
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
2181-
SplatPat_simm5_plus1>;
2182-
defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
2183-
SplatPat_simm5_plus1_nonzero>;
2152+
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLT, SETGT,
2153+
SplatPat_simm5_plus1>;
2154+
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
2155+
SplatPat_simm5_plus1_nonzero>;
2156+
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGE, SETLE,
2157+
SplatPat_simm5_plus1>;
2158+
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
2159+
SplatPat_simm5_plus1_nonzero>;
21842160
}
21852161
} // foreach vti = AllIntegerVectors
21862162

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