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davemgreendavemgreen
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[AArch64] Alter latency of FCSEL under Cortex-A510 (#80178)
As per the Cortex-A510 software optimization guide, the latency of a fcsel should be 3 not 4. It would previously get the latency from WriteF.
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6 files changed

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-154
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6 files changed

+156
-154
lines changed

‎llvm/lib/Target/AArch64/AArch64SchedA510.td‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -394,6 +394,8 @@ def : InstRW<[CortexA510WriteFSqrtHP], (instregex "^.*SQRT.*16$")>;
394394
def : InstRW<[CortexA510WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
395395
def : InstRW<[CortexA510WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
396396

397+
def : InstRW<[CortexA510WriteFPALU_F3], (instrs FCSELHrrr, FCSELSrrr, FCSELDrrr)>;
398+
397399
// 4.15. Advanced SIMD integer instructions
398400
// ASIMD absolute diff
399401
def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>], (instregex "[SU]ABDv(2i32|4i16|8i8)")>;

‎llvm/test/CodeGen/AArch64/select_fmf.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -9,11 +9,11 @@ define float @select_select_fold_select_and(float %w, float %x, float %y, float
99
; CHECK: // %bb.0:
1010
; CHECK-NEXT: fminnm s4, s1, s2
1111
; CHECK-NEXT: fcmp s1, s2
12-
; CHECK-NEXT: fmaxnm s1, s0, s3
12+
; CHECK-NEXT: fmaxnm s2, s0, s3
13+
; CHECK-NEXT: fmov s1, #0.50000000
1314
; CHECK-NEXT: fccmp s4, s0, #4, lt
14-
; CHECK-NEXT: fmov s4, #0.50000000
15-
; CHECK-NEXT: fcsel s2, s1, s0, gt
16-
; CHECK-NEXT: fadd s1, s0, s4
15+
; CHECK-NEXT: fadd s1, s0, s1
16+
; CHECK-NEXT: fcsel s2, s2, s0, gt
1717
; CHECK-NEXT: fadd s4, s1, s2
1818
; CHECK-NEXT: fcmp s4, s1
1919
; CHECK-NEXT: b.le .LBB0_2
@@ -67,11 +67,11 @@ define float @select_select_fold_select_or(float %w, float %x, float %y, float %
6767
; CHECK: // %bb.0:
6868
; CHECK-NEXT: fminnm s4, s1, s2
6969
; CHECK-NEXT: fcmp s1, s2
70-
; CHECK-NEXT: fmaxnm s1, s0, s3
70+
; CHECK-NEXT: fmaxnm s2, s0, s3
71+
; CHECK-NEXT: fmov s1, #0.50000000
7172
; CHECK-NEXT: fccmp s4, s0, #0, ge
72-
; CHECK-NEXT: fmov s4, #0.50000000
73-
; CHECK-NEXT: fcsel s2, s0, s1, gt
74-
; CHECK-NEXT: fadd s1, s0, s4
73+
; CHECK-NEXT: fadd s1, s0, s1
74+
; CHECK-NEXT: fcsel s2, s0, s2, gt
7575
; CHECK-NEXT: fadd s4, s1, s2
7676
; CHECK-NEXT: fcmp s4, s1
7777
; CHECK-NEXT: b.le .LBB1_2

‎llvm/test/CodeGen/AArch64/tbl-loops.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -562,25 +562,25 @@ define void @loop4(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
562562
; CHECK-NEXT: fcmp s3, s1
563563
; CHECK-NEXT: fcsel s4, s1, s3, gt
564564
; CHECK-NEXT: fcmp s3, #0.0
565-
; CHECK-NEXT: ldp s3, s5, [x8, #8]
566565
; CHECK-NEXT: fcvtzs w11, s2
566+
; CHECK-NEXT: ldp s3, s5, [x8, #8]
567567
; CHECK-NEXT: add x8, x8, #16
568568
; CHECK-NEXT: fcsel s4, s0, s4, mi
569569
; CHECK-NEXT: fcmp s3, s1
570570
; CHECK-NEXT: strb w11, [x9]
571+
; CHECK-NEXT: fcvtzs w12, s4
571572
; CHECK-NEXT: fcsel s6, s1, s3, gt
572573
; CHECK-NEXT: fcmp s3, #0.0
573-
; CHECK-NEXT: fcvtzs w12, s4
574574
; CHECK-NEXT: fcsel s3, s0, s6, mi
575575
; CHECK-NEXT: fcmp s5, s1
576576
; CHECK-NEXT: strb w12, [x9, #1]
577577
; CHECK-NEXT: fcsel s6, s1, s5, gt
578578
; CHECK-NEXT: fcmp s5, #0.0
579579
; CHECK-NEXT: fcvtzs w13, s3
580-
; CHECK-NEXT: fcsel s5, s0, s6, mi
580+
; CHECK-NEXT: fcsel s2, s0, s6, mi
581581
; CHECK-NEXT: subs w10, w10, #1
582582
; CHECK-NEXT: strb w13, [x9, #2]
583-
; CHECK-NEXT: fcvtzs w14, s5
583+
; CHECK-NEXT: fcvtzs w14, s2
584584
; CHECK-NEXT: strb w14, [x9, #3]
585585
; CHECK-NEXT: add x9, x9, #4
586586
; CHECK-NEXT: b.ne .LBB3_6

‎llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll‎

Lines changed: 70 additions & 70 deletions
Original file line numberDiff line numberDiff line change
@@ -242,59 +242,59 @@ define half @test_v16f16(<16 x half> %a) nounwind {
242242
; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
243243
; CHECK-NOFP-SD-NEXT: mov h4, v1.h[3]
244244
; CHECK-NOFP-SD-NEXT: mov h5, v0.h[3]
245-
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
246245
; CHECK-NOFP-SD-NEXT: fcvt h3, s3
246+
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
247247
; CHECK-NOFP-SD-NEXT: fcvt s4, h4
248248
; CHECK-NOFP-SD-NEXT: fcvt s5, h5
249-
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
250249
; CHECK-NOFP-SD-NEXT: fcvt s3, h3
250+
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
251251
; CHECK-NOFP-SD-NEXT: fcmp s5, s4
252252
; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
253253
; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
254254
; CHECK-NOFP-SD-NEXT: mov h4, v1.h[4]
255255
; CHECK-NOFP-SD-NEXT: mov h5, v0.h[4]
256-
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
257256
; CHECK-NOFP-SD-NEXT: fcvt h3, s3
257+
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
258258
; CHECK-NOFP-SD-NEXT: fcvt s4, h4
259259
; CHECK-NOFP-SD-NEXT: fcvt s5, h5
260-
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
261260
; CHECK-NOFP-SD-NEXT: fcvt s3, h3
261+
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
262262
; CHECK-NOFP-SD-NEXT: fcmp s5, s4
263263
; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
264264
; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
265265
; CHECK-NOFP-SD-NEXT: mov h4, v1.h[5]
266266
; CHECK-NOFP-SD-NEXT: mov h5, v0.h[5]
267-
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
268267
; CHECK-NOFP-SD-NEXT: fcvt h3, s3
268+
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
269269
; CHECK-NOFP-SD-NEXT: fcvt s4, h4
270270
; CHECK-NOFP-SD-NEXT: fcvt s5, h5
271-
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
272271
; CHECK-NOFP-SD-NEXT: fcvt s3, h3
272+
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
273273
; CHECK-NOFP-SD-NEXT: fcmp s5, s4
274274
; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
275275
; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
276276
; CHECK-NOFP-SD-NEXT: mov h4, v1.h[6]
277277
; CHECK-NOFP-SD-NEXT: mov h5, v0.h[6]
278278
; CHECK-NOFP-SD-NEXT: mov h1, v1.h[7]
279279
; CHECK-NOFP-SD-NEXT: mov h0, v0.h[7]
280-
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
281280
; CHECK-NOFP-SD-NEXT: fcvt h3, s3
281+
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
282282
; CHECK-NOFP-SD-NEXT: fcvt s4, h4
283283
; CHECK-NOFP-SD-NEXT: fcvt s5, h5
284284
; CHECK-NOFP-SD-NEXT: fcvt s1, h1
285285
; CHECK-NOFP-SD-NEXT: fcvt s0, h0
286-
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
287286
; CHECK-NOFP-SD-NEXT: fcvt s3, h3
287+
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
288288
; CHECK-NOFP-SD-NEXT: fcmp s5, s4
289289
; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
290290
; CHECK-NOFP-SD-NEXT: fcsel s3, s5, s4, gt
291291
; CHECK-NOFP-SD-NEXT: fcmp s0, s1
292+
; CHECK-NOFP-SD-NEXT: fcvt h3, s3
292293
; CHECK-NOFP-SD-NEXT: fcsel s0, s0, s1, gt
293294
; CHECK-NOFP-SD-NEXT: fcvt h2, s2
294-
; CHECK-NOFP-SD-NEXT: fcvt h3, s3
295295
; CHECK-NOFP-SD-NEXT: fcvt h0, s0
296-
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
297296
; CHECK-NOFP-SD-NEXT: fcvt s3, h3
297+
; CHECK-NOFP-SD-NEXT: fcvt s2, h2
298298
; CHECK-NOFP-SD-NEXT: fcvt s0, h0
299299
; CHECK-NOFP-SD-NEXT: fmaxnm s2, s2, s3
300300
; CHECK-NOFP-SD-NEXT: fcvt h1, s2
@@ -420,66 +420,66 @@ define half @test_v11f16(<11 x half> %a) nounwind {
420420
; CHECK-NOFP-NEXT: fcvt s16, h16
421421
; CHECK-NOFP-NEXT: fcvt s17, h17
422422
; CHECK-NOFP-NEXT: fcvt s3, h3
423+
; CHECK-NOFP-NEXT: fcvt s4, h4
423424
; CHECK-NOFP-NEXT: fcmp s1, s16
424425
; CHECK-NOFP-NEXT: fcsel s1, s1, s16, gt
425426
; CHECK-NOFP-NEXT: fcmp s0, s17
426427
; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
427428
; CHECK-NOFP-NEXT: fcvt s16, h16
428429
; CHECK-NOFP-NEXT: fcsel s0, s0, s17, gt
429430
; CHECK-NOFP-NEXT: fcvt h1, s1
430-
; CHECK-NOFP-NEXT: fcmp s2, s16
431431
; CHECK-NOFP-NEXT: fcvt h0, s0
432+
; CHECK-NOFP-NEXT: fcmp s2, s16
432433
; CHECK-NOFP-NEXT: fcvt s1, h1
433434
; CHECK-NOFP-NEXT: fcvt s0, h0
434435
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
435436
; CHECK-NOFP-NEXT: fcsel s1, s2, s16, gt
436437
; CHECK-NOFP-NEXT: ldr h2, [x8, :lo12:.LCPI14_0]
437438
; CHECK-NOFP-NEXT: mov w8, #-8388608 // =0xff800000
438439
; CHECK-NOFP-NEXT: fcvt s2, h2
439-
; CHECK-NOFP-NEXT: fmov s16, w8
440-
; CHECK-NOFP-NEXT: fcvt h0, s0
441440
; CHECK-NOFP-NEXT: fcvt h1, s1
441+
; CHECK-NOFP-NEXT: fcvt h0, s0
442442
; CHECK-NOFP-NEXT: fcmp s3, s2
443-
; CHECK-NOFP-NEXT: fcvt s0, h0
444443
; CHECK-NOFP-NEXT: fcvt s1, h1
444+
; CHECK-NOFP-NEXT: fcvt s0, h0
445445
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
446-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
447-
; CHECK-NOFP-NEXT: fcvt s3, h4
446+
; CHECK-NOFP-NEXT: fmov s1, w8
447+
; CHECK-NOFP-NEXT: fcsel s3, s3, s1, gt
448+
; CHECK-NOFP-NEXT: fcmp s4, s2
448449
; CHECK-NOFP-NEXT: fcvt h0, s0
449-
; CHECK-NOFP-NEXT: fcvt h1, s1
450-
; CHECK-NOFP-NEXT: fcmp s3, s2
450+
; CHECK-NOFP-NEXT: fcvt h3, s3
451451
; CHECK-NOFP-NEXT: fcvt s0, h0
452-
; CHECK-NOFP-NEXT: fcvt s1, h1
453-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
454-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
455-
; CHECK-NOFP-NEXT: fcvt s3, h5
452+
; CHECK-NOFP-NEXT: fcvt s3, h3
453+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
454+
; CHECK-NOFP-NEXT: fcsel s3, s4, s1, gt
455+
; CHECK-NOFP-NEXT: fcvt s4, h5
456+
; CHECK-NOFP-NEXT: fcvt h3, s3
456457
; CHECK-NOFP-NEXT: fcvt h0, s0
457-
; CHECK-NOFP-NEXT: fcvt h1, s1
458-
; CHECK-NOFP-NEXT: fcmp s3, s2
458+
; CHECK-NOFP-NEXT: fcmp s4, s2
459+
; CHECK-NOFP-NEXT: fcvt s3, h3
459460
; CHECK-NOFP-NEXT: fcvt s0, h0
460-
; CHECK-NOFP-NEXT: fcvt s1, h1
461-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
462-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
463-
; CHECK-NOFP-NEXT: fcvt s3, h6
461+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
462+
; CHECK-NOFP-NEXT: fcsel s3, s4, s1, gt
463+
; CHECK-NOFP-NEXT: fcvt s4, h6
464+
; CHECK-NOFP-NEXT: fcvt h3, s3
464465
; CHECK-NOFP-NEXT: fcvt h0, s0
465-
; CHECK-NOFP-NEXT: fcvt h1, s1
466-
; CHECK-NOFP-NEXT: fcmp s3, s2
466+
; CHECK-NOFP-NEXT: fcmp s4, s2
467+
; CHECK-NOFP-NEXT: fcvt s3, h3
467468
; CHECK-NOFP-NEXT: fcvt s0, h0
468-
; CHECK-NOFP-NEXT: fcvt s1, h1
469-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
470-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
471-
; CHECK-NOFP-NEXT: fcvt s3, h7
469+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
470+
; CHECK-NOFP-NEXT: fcsel s3, s4, s1, gt
471+
; CHECK-NOFP-NEXT: fcvt s4, h7
472+
; CHECK-NOFP-NEXT: fcvt h3, s3
472473
; CHECK-NOFP-NEXT: fcvt h0, s0
473-
; CHECK-NOFP-NEXT: fcvt h1, s1
474-
; CHECK-NOFP-NEXT: fcmp s3, s2
474+
; CHECK-NOFP-NEXT: fcmp s4, s2
475+
; CHECK-NOFP-NEXT: fcvt s3, h3
476+
; CHECK-NOFP-NEXT: fcsel s1, s4, s1, gt
475477
; CHECK-NOFP-NEXT: fcvt s0, h0
478+
; CHECK-NOFP-NEXT: fcvt h1, s1
479+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
476480
; CHECK-NOFP-NEXT: fcvt s1, h1
477-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
478-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
479481
; CHECK-NOFP-NEXT: fcvt h0, s0
480-
; CHECK-NOFP-NEXT: fcvt h1, s1
481482
; CHECK-NOFP-NEXT: fcvt s0, h0
482-
; CHECK-NOFP-NEXT: fcvt s1, h1
483483
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
484484
; CHECK-NOFP-NEXT: fcvt h0, s0
485485
; CHECK-NOFP-NEXT: ret
@@ -527,15 +527,16 @@ define half @test_v11f16_ninf(<11 x half> %a) nounwind {
527527
; CHECK-NOFP-NEXT: fcvt s16, h16
528528
; CHECK-NOFP-NEXT: fcvt s17, h17
529529
; CHECK-NOFP-NEXT: fcvt s3, h3
530+
; CHECK-NOFP-NEXT: fcvt s4, h4
530531
; CHECK-NOFP-NEXT: fcmp s1, s16
531532
; CHECK-NOFP-NEXT: fcsel s1, s1, s16, gt
532533
; CHECK-NOFP-NEXT: fcmp s0, s17
533534
; CHECK-NOFP-NEXT: ldr h16, [sp, #16]
534535
; CHECK-NOFP-NEXT: fcvt s16, h16
535536
; CHECK-NOFP-NEXT: fcsel s0, s0, s17, gt
536537
; CHECK-NOFP-NEXT: fcvt h1, s1
537-
; CHECK-NOFP-NEXT: fcmp s2, s16
538538
; CHECK-NOFP-NEXT: fcvt h0, s0
539+
; CHECK-NOFP-NEXT: fcmp s2, s16
539540
; CHECK-NOFP-NEXT: fcvt s1, h1
540541
; CHECK-NOFP-NEXT: fcvt s0, h0
541542
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
@@ -544,50 +545,49 @@ define half @test_v11f16_ninf(<11 x half> %a) nounwind {
544545
; CHECK-NOFP-NEXT: mov w8, #57344 // =0xe000
545546
; CHECK-NOFP-NEXT: fcvt s2, h2
546547
; CHECK-NOFP-NEXT: movk w8, #51071, lsl #16
547-
; CHECK-NOFP-NEXT: fmov s16, w8
548-
; CHECK-NOFP-NEXT: fcvt h0, s0
549548
; CHECK-NOFP-NEXT: fcvt h1, s1
549+
; CHECK-NOFP-NEXT: fcvt h0, s0
550550
; CHECK-NOFP-NEXT: fcmp s3, s2
551-
; CHECK-NOFP-NEXT: fcvt s0, h0
552551
; CHECK-NOFP-NEXT: fcvt s1, h1
552+
; CHECK-NOFP-NEXT: fcvt s0, h0
553553
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
554-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
555-
; CHECK-NOFP-NEXT: fcvt s3, h4
554+
; CHECK-NOFP-NEXT: fmov s1, w8
555+
; CHECK-NOFP-NEXT: fcsel s3, s3, s1, gt
556+
; CHECK-NOFP-NEXT: fcmp s4, s2
556557
; CHECK-NOFP-NEXT: fcvt h0, s0
557-
; CHECK-NOFP-NEXT: fcvt h1, s1
558-
; CHECK-NOFP-NEXT: fcmp s3, s2
558+
; CHECK-NOFP-NEXT: fcvt h3, s3
559559
; CHECK-NOFP-NEXT: fcvt s0, h0
560-
; CHECK-NOFP-NEXT: fcvt s1, h1
561-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
562-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
563-
; CHECK-NOFP-NEXT: fcvt s3, h5
560+
; CHECK-NOFP-NEXT: fcvt s3, h3
561+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
562+
; CHECK-NOFP-NEXT: fcsel s3, s4, s1, gt
563+
; CHECK-NOFP-NEXT: fcvt s4, h5
564+
; CHECK-NOFP-NEXT: fcvt h3, s3
564565
; CHECK-NOFP-NEXT: fcvt h0, s0
565-
; CHECK-NOFP-NEXT: fcvt h1, s1
566-
; CHECK-NOFP-NEXT: fcmp s3, s2
566+
; CHECK-NOFP-NEXT: fcmp s4, s2
567+
; CHECK-NOFP-NEXT: fcvt s3, h3
567568
; CHECK-NOFP-NEXT: fcvt s0, h0
568-
; CHECK-NOFP-NEXT: fcvt s1, h1
569-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
570-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
571-
; CHECK-NOFP-NEXT: fcvt s3, h6
569+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
570+
; CHECK-NOFP-NEXT: fcsel s3, s4, s1, gt
571+
; CHECK-NOFP-NEXT: fcvt s4, h6
572+
; CHECK-NOFP-NEXT: fcvt h3, s3
572573
; CHECK-NOFP-NEXT: fcvt h0, s0
573-
; CHECK-NOFP-NEXT: fcvt h1, s1
574-
; CHECK-NOFP-NEXT: fcmp s3, s2
574+
; CHECK-NOFP-NEXT: fcmp s4, s2
575+
; CHECK-NOFP-NEXT: fcvt s3, h3
575576
; CHECK-NOFP-NEXT: fcvt s0, h0
576-
; CHECK-NOFP-NEXT: fcvt s1, h1
577-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
578-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
579-
; CHECK-NOFP-NEXT: fcvt s3, h7
577+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
578+
; CHECK-NOFP-NEXT: fcsel s3, s4, s1, gt
579+
; CHECK-NOFP-NEXT: fcvt s4, h7
580+
; CHECK-NOFP-NEXT: fcvt h3, s3
580581
; CHECK-NOFP-NEXT: fcvt h0, s0
581-
; CHECK-NOFP-NEXT: fcvt h1, s1
582-
; CHECK-NOFP-NEXT: fcmp s3, s2
582+
; CHECK-NOFP-NEXT: fcmp s4, s2
583+
; CHECK-NOFP-NEXT: fcvt s3, h3
584+
; CHECK-NOFP-NEXT: fcsel s1, s4, s1, gt
583585
; CHECK-NOFP-NEXT: fcvt s0, h0
586+
; CHECK-NOFP-NEXT: fcvt h1, s1
587+
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s3
584588
; CHECK-NOFP-NEXT: fcvt s1, h1
585-
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
586-
; CHECK-NOFP-NEXT: fcsel s1, s3, s16, gt
587589
; CHECK-NOFP-NEXT: fcvt h0, s0
588-
; CHECK-NOFP-NEXT: fcvt h1, s1
589590
; CHECK-NOFP-NEXT: fcvt s0, h0
590-
; CHECK-NOFP-NEXT: fcvt s1, h1
591591
; CHECK-NOFP-NEXT: fmaxnm s0, s0, s1
592592
; CHECK-NOFP-NEXT: fcvt h0, s0
593593
; CHECK-NOFP-NEXT: ret

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