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[AArch64] computeKnownBitsForTargetNode - add AArch64ISD::MOVIshift support (#148634)
Fixes #148596
1 parent ae810dd commit 5d59cb6

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5 files changed

+44
-44
lines changed

5 files changed

+44
-44
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2600,6 +2600,12 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
26002600
APInt(Known.getBitWidth(), Op->getConstantOperandVal(0)));
26012601
break;
26022602
}
2603+
case AArch64ISD::MOVIshift: {
2604+
Known = KnownBits::makeConstant(
2605+
APInt(Known.getBitWidth(), Op->getConstantOperandVal(0)
2606+
<< Op->getConstantOperandVal(1)));
2607+
break;
2608+
}
26032609
case AArch64ISD::LOADgot:
26042610
case AArch64ISD::ADDlow: {
26052611
if (!Subtarget->isTargetILP32())
@@ -30287,6 +30293,7 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
3028730293
bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
3028830294
return Op.getOpcode() == AArch64ISD::DUP ||
3028930295
Op.getOpcode() == AArch64ISD::MOVI ||
30296+
Op.getOpcode() == AArch64ISD::MOVIshift ||
3029030297
(Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
3029130298
Op.getOperand(0).getOpcode() == AArch64ISD::DUP) ||
3029230299
TargetLowering::isTargetCanonicalConstantNode(Op);

‎llvm/test/CodeGen/AArch64/arm64-zip.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -454,7 +454,7 @@ define <4 x i32> @shuffle_zip3(<4 x i32> %arg) {
454454
; CHECK-NEXT: zip2.4h v0, v0, v1
455455
; CHECK-NEXT: movi.4s v1, #1
456456
; CHECK-NEXT: zip1.4h v0, v0, v0
457-
; CHECK-NEXT: sshll.4s v0, v0, #0
457+
; CHECK-NEXT: ushll.4s v0, v0, #0
458458
; CHECK-NEXT: and.16b v0, v0, v1
459459
; CHECK-NEXT: ret
460460
bb:

‎llvm/test/CodeGen/AArch64/combine-mul.ll

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -28,10 +28,7 @@ define <4 x i1> @PR48683_vec(<4 x i32> %x) {
2828
define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) {
2929
; CHECK-LABEL: PR48683_vec_undef:
3030
; CHECK: // %bb.0:
31-
; CHECK-NEXT: movi v1.4s, #2
32-
; CHECK-NEXT: mul v0.4s, v0.4s, v0.4s
33-
; CHECK-NEXT: cmtst v0.4s, v0.4s, v1.4s
34-
; CHECK-NEXT: xtn v0.4h, v0.4s
31+
; CHECK-NEXT: movi v0.2d, #0000000000000000
3532
; CHECK-NEXT: ret
3633
%a = mul <4 x i32> %x, %x
3734
%b = and <4 x i32> %a, <i32 2, i32 2, i32 2, i32 undef>

‎llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,6 @@ define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) {
2626
; CHECK-LABEL: icmp_constfold_v2i32:
2727
; CHECK: ; %bb.0:
2828
; CHECK-NEXT: movi.2s v0, #1
29-
; CHECK-NEXT: and.8b v0, v0, v0
3029
; CHECK-NEXT: ret
3130
%1 = icmp eq <2 x i32> %a, %a
3231
br label %bb2
@@ -56,8 +55,6 @@ define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) {
5655
; CHECK-LABEL: icmp_constfold_v4i32:
5756
; CHECK: ; %bb.0:
5857
; CHECK-NEXT: movi.4h v0, #1
59-
; CHECK-NEXT: ; %bb.1: ; %bb2
60-
; CHECK-NEXT: and.8b v0, v0, v0
6158
; CHECK-NEXT: ushll.4s v0, v0, #0
6259
; CHECK-NEXT: ret
6360
%1 = icmp eq <4 x i32> %a, %a

‎llvm/test/CodeGen/AArch64/zext-to-tbl.ll

Lines changed: 35 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1246,33 +1246,33 @@ define void @zext_v16i4_to_v16i32_in_loop(ptr %src, ptr %dst) {
12461246
; CHECK-NEXT: add x8, x8, #16
12471247
; CHECK-NEXT: cmp x8, #128
12481248
; CHECK-NEXT: ubfx x12, x9, #48, #4
1249-
; CHECK-NEXT: ubfx x10, x9, #52, #4
1250-
; CHECK-NEXT: ubfx x14, x9, #32, #4
1249+
; CHECK-NEXT: lsr x10, x9, #52
1250+
; CHECK-NEXT: ubfx x13, x9, #32, #4
12511251
; CHECK-NEXT: ubfx w15, w9, #16, #4
1252-
; CHECK-NEXT: ubfx x11, x9, #36, #4
1253-
; CHECK-NEXT: ubfx w13, w9, #20, #4
1252+
; CHECK-NEXT: lsr x11, x9, #36
1253+
; CHECK-NEXT: lsr w14, w9, #20
12541254
; CHECK-NEXT: fmov s1, w12
1255-
; CHECK-NEXT: fmov s2, w14
1256-
; CHECK-NEXT: ubfx w12, w9, #4, #4
1255+
; CHECK-NEXT: fmov s2, w13
1256+
; CHECK-NEXT: lsr w12, w9, #4
12571257
; CHECK-NEXT: fmov s3, w15
12581258
; CHECK-NEXT: mov.h v1[1], w10
12591259
; CHECK-NEXT: and w10, w9, #0xf
12601260
; CHECK-NEXT: mov.h v2[1], w11
12611261
; CHECK-NEXT: fmov s4, w10
1262-
; CHECK-NEXT: ubfx x11, x9, #56, #4
1263-
; CHECK-NEXT: mov.h v3[1], w13
1264-
; CHECK-NEXT: ubfx x10, x9, #40, #4
1262+
; CHECK-NEXT: lsr x11, x9, #56
1263+
; CHECK-NEXT: mov.h v3[1], w14
1264+
; CHECK-NEXT: lsr x10, x9, #40
12651265
; CHECK-NEXT: mov.h v4[1], w12
1266-
; CHECK-NEXT: ubfx w12, w9, #24, #4
1266+
; CHECK-NEXT: lsr w12, w9, #24
12671267
; CHECK-NEXT: mov.h v1[2], w11
1268-
; CHECK-NEXT: ubfx w11, w9, #8, #4
1268+
; CHECK-NEXT: lsr w11, w9, #8
12691269
; CHECK-NEXT: mov.h v2[2], w10
12701270
; CHECK-NEXT: lsr x10, x9, #60
12711271
; CHECK-NEXT: mov.h v3[2], w12
1272-
; CHECK-NEXT: ubfx x12, x9, #44, #4
1272+
; CHECK-NEXT: lsr x12, x9, #44
12731273
; CHECK-NEXT: mov.h v4[2], w11
12741274
; CHECK-NEXT: lsr w11, w9, #28
1275-
; CHECK-NEXT: ubfx w9, w9, #12, #4
1275+
; CHECK-NEXT: lsr w9, w9, #12
12761276
; CHECK-NEXT: mov.h v1[3], w10
12771277
; CHECK-NEXT: mov.h v2[3], w12
12781278
; CHECK-NEXT: mov.h v3[3], w11
@@ -1300,38 +1300,37 @@ define void @zext_v16i4_to_v16i32_in_loop(ptr %src, ptr %dst) {
13001300
; CHECK-BE-NEXT: ldr x9, [x0, x8]
13011301
; CHECK-BE-NEXT: add x8, x8, #16
13021302
; CHECK-BE-NEXT: cmp x8, #128
1303-
; CHECK-BE-NEXT: ubfx w12, w9, #12, #4
1303+
; CHECK-BE-NEXT: ubfx w11, w9, #12, #4
13041304
; CHECK-BE-NEXT: lsr w14, w9, #28
1305-
; CHECK-BE-NEXT: ubfx w10, w9, #8, #4
1305+
; CHECK-BE-NEXT: lsr w10, w9, #8
13061306
; CHECK-BE-NEXT: ubfx x15, x9, #44, #4
1307-
; CHECK-BE-NEXT: ubfx w11, w9, #24, #4
1308-
; CHECK-BE-NEXT: ubfx x13, x9, #40, #4
1309-
; CHECK-BE-NEXT: fmov s1, w12
1310-
; CHECK-BE-NEXT: lsr x12, x9, #60
1307+
; CHECK-BE-NEXT: lsr w12, w9, #24
1308+
; CHECK-BE-NEXT: lsr x13, x9, #40
1309+
; CHECK-BE-NEXT: fmov s1, w11
1310+
; CHECK-BE-NEXT: lsr x11, x9, #60
13111311
; CHECK-BE-NEXT: fmov s2, w14
13121312
; CHECK-BE-NEXT: fmov s3, w15
1313-
; CHECK-BE-NEXT: fmov s4, w12
1314-
; CHECK-BE-NEXT: ubfx w12, w9, #20, #4
1313+
; CHECK-BE-NEXT: fmov s4, w11
1314+
; CHECK-BE-NEXT: lsr w11, w9, #20
13151315
; CHECK-BE-NEXT: mov v1.h[1], w10
1316-
; CHECK-BE-NEXT: ubfx x10, x9, #56, #4
1317-
; CHECK-BE-NEXT: mov v2.h[1], w11
1318-
; CHECK-BE-NEXT: ubfx w11, w9, #4, #4
1316+
; CHECK-BE-NEXT: lsr x10, x9, #56
1317+
; CHECK-BE-NEXT: mov v2.h[1], w12
1318+
; CHECK-BE-NEXT: lsr w12, w9, #4
13191319
; CHECK-BE-NEXT: mov v3.h[1], w13
13201320
; CHECK-BE-NEXT: mov v4.h[1], w10
1321-
; CHECK-BE-NEXT: ubfx x10, x9, #36, #4
1322-
; CHECK-BE-NEXT: mov v1.h[2], w11
1323-
; CHECK-BE-NEXT: ubfx x11, x9, #52, #4
1324-
; CHECK-BE-NEXT: mov v2.h[2], w12
1321+
; CHECK-BE-NEXT: lsr x10, x9, #36
1322+
; CHECK-BE-NEXT: mov v1.h[2], w12
1323+
; CHECK-BE-NEXT: lsr x12, x9, #52
1324+
; CHECK-BE-NEXT: mov v2.h[2], w11
13251325
; CHECK-BE-NEXT: mov v3.h[2], w10
1326-
; CHECK-BE-NEXT: and w10, w9, #0xf
1327-
; CHECK-BE-NEXT: ubfx w12, w9, #16, #4
1328-
; CHECK-BE-NEXT: mov v4.h[2], w11
1329-
; CHECK-BE-NEXT: ubfx x11, x9, #32, #4
1330-
; CHECK-BE-NEXT: ubfx x9, x9, #48, #4
1331-
; CHECK-BE-NEXT: mov v1.h[3], w10
1332-
; CHECK-BE-NEXT: mov v2.h[3], w12
1333-
; CHECK-BE-NEXT: add x10, x1, #32
1326+
; CHECK-BE-NEXT: lsr w10, w9, #16
1327+
; CHECK-BE-NEXT: lsr x11, x9, #32
1328+
; CHECK-BE-NEXT: mov v4.h[2], w12
1329+
; CHECK-BE-NEXT: mov v1.h[3], w9
1330+
; CHECK-BE-NEXT: lsr x9, x9, #48
1331+
; CHECK-BE-NEXT: mov v2.h[3], w10
13341332
; CHECK-BE-NEXT: mov v3.h[3], w11
1333+
; CHECK-BE-NEXT: add x10, x1, #32
13351334
; CHECK-BE-NEXT: mov v4.h[3], w9
13361335
; CHECK-BE-NEXT: add x9, x1, #48
13371336
; CHECK-BE-NEXT: ushll v1.4s, v1.4h, #0

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