[PowerPC] Replace vspltisw instruction with xxleqv as generation of vector of -1s is cheaper than vector of 1s

Author: himadhith

llvm/lib/Target/PowerPC/PPCInstrVSX.td

@@ -3627,6 +3627,10 @@ def : Pat<(v4i32 (build_vector immSExt5NonZero:$A, immSExt5NonZero:$A,
                                immSExt5NonZero:$A, immSExt5NonZero:$A)),
           (v4i32 (VSPLTISW imm:$A))>;
 
+// Optimize for vector of 1s addition operation
+def : Pat<(add v4i32:$A, (build_vector (i32 1), (i32 1), (i32 1), (i32 1))),
+          (VSUBUWM $A, (v4i32 (COPY_TO_REGCLASS (XXLEQVOnes), VSRC)))>;
+
 // Splat loads.
 def : Pat<(v8i16 (PPCldsplat ForceXForm:$A)),
           (v8i16 (VSPLTHs 3, (MTVSRWZ (LHZX ForceXForm:$A))))>;

llvm/test/CodeGen/PowerPC/vector-all-ones.ll

@@ -0,0 +1,32 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64LE
+
+; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc64-ibm-aix \
+; RUN:     -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_64
+
+; RUN: llc -verify-machineinstrs -O3 -mcpu=pwr9 -mtriple=powerpc-ibm-aix \
+; RUN:     -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=POWERPC_32
+
+define dso_local noundef <4 x i32> @test1(<4 x i32> %a) {
+; POWERPC_64LE-LABEL: test1:
+; POWERPC_64LE:       # %bb.0: # %entry
+; POWERPC_64LE-NEXT:    xxleqv v3, v3, v3
+; POWERPC_64LE-NEXT:    vsubuwm v2, v2, v3
+; POWERPC_64LE-NEXT:    blr
+;
+; POWERPC_64-LABEL: test1:
+; POWERPC_64:       # %bb.0: # %entry
+; POWERPC_64-NEXT:    xxleqv v3, v3, v3
+; POWERPC_64-NEXT:    vsubuwm v2, v2, v3
+; POWERPC_64-NEXT:    blr
+;
+; POWERPC_32-LABEL: test1:
+; POWERPC_32:       # %bb.0: # %entry
+; POWERPC_32-NEXT:    xxleqv v3, v3, v3
+; POWERPC_32-NEXT:    vsubuwm v2, v2, v3
+; POWERPC_32-NEXT:    blr
+entry:
+  %add = add <4 x i32> %a, splat (i32 1)
+  ret <4 x i32> %add
+}